In-memory eigenvector computation in time O(1)

In-memory computing with crosspoint resistive memory arrays has gained enormous attention to accelerate the matrix-vector multiplication in the computation of data-centric applications. By combining a crosspoint array and feedback amplifiers, it is possible to compute matrix eigenvectors in one step without algorithmic iterations. In this work, time complexity of the eigenvector computation is investigated, based on the feedback analysis of the crosspoint circuit. The results show that the computing time of the circuit is determined by the mismatch degree of the eigenvalues implemented in the circuit, which controls the rising speed of output voltages. For a dataset of random matrices, the time for computing the dominant eigenvector in the circuit is constant for various matrix sizes, namely the time complexity is O(1). The O(1) time complexity is also supported by simulations of PageRank of real-world datasets. This work paves the way for fast, energy-efficient accelerators for eigenvector computation in a wide range of practical applications.Comment: Accepted by Adv. Intell. Sys

Memtransistor Devices Based on MoS 2 Multilayers with Volatile Switching due to Ag Cation Migration

In the recent years, the need for fast, robust, and scalable memory devices have spurred the exploration of advanced materials with unique electrical properties. Among these materials, 2D semiconductors are promising candidates as they combine atomically thin size, semiconductor behavior, and complementary metal-oxide-semiconductor compatibility. Here a three-terminal memtransistor device, based on multilayer MoS2 with ultrashort channel length, that combines the usual transistor behavior of 2D semiconductors with resistive switching memory operation is presented. The volatile switching behavior is explained by the Ag cation migration along the channel surface. An extensive physical and electrical characterization to investigate the fundamental properties of the device, is presented. Finally, a chain-type memory array architecture similar to a NAND flash structure consisting of memtransistors is demonstrated, where the individual memory devices can be selected for write and read, paving the way for high-density, 3D memories based on 2D semiconductors

Time complexity of in-memory solution of linear systems

In-memory computing with crosspoint resistive memory arrays has been shown to accelerate data-centric computations such as the training and inference of deep neural networks, thanks to the high parallelism endowed by physical rules in the electrical circuits. By connecting crosspoint arrays with negative feedback amplifiers, it is possible to solve linear algebraic problems such as linear systems and matrix eigenvectors in just one step. Based on the theory of feedback circuits, we study the dynamics of the solution of linear systems within a memory array, showing that the time complexity of the solution is free of any direct dependence on the problem size N, rather it is governed by the minimal eigenvalue of an associated matrix of the coefficient matrix. We show that, when the linear system is modeled by a covariance matrix, the time complexity is O(logN) or O(1). In the case of sparse positive-definite linear systems, the time complexity is solely determined by the minimal eigenvalue of the coefficient matrix. These results demonstrate the high speed of the circuit for solving linear systems in a wide range of applications, thus supporting in-memory computing as a strong candidate for future big data and machine learning accelerators.Comment: Accepted by IEEE Trans. Electron Devices. The authors thank Scott Aaronson for helpful discussion about time complexit

Experimental Demonstration of Non-Stateful In-Memory Logic with 1T1R OxRAM Valence Change Mechanism Memristors

Processing-in-memory (PIM) is attractive to overcome the limitations of modern computing systems. Numerous PIM systems exist, varying by the technologies and logic techniques used. Successful operation of specific logic functions is crucial for effective processing-in-memory. Memristive non-stateful logic techniques are compatible with CMOS logic and can be integrated into a 1T1R memory array, similar to commercial RRAM products. This paper analyzes and demonstrates two non-stateful logic techniques: 1T1R logic and scouting logic. As a first step, the used 1T1R SiO\textsubscript{x} valence change mechanism memristors are characterized in reference to their feasibility to perform logic functions. Various logical functions of the two logic techniques are experimentally demonstrated, showing correct functionality in all cases. Following the results, the challenges and limitations of the RRAM characteristics and 1T1R configuration for the application in logical functions are discussed.Comment: 5 pages, 6 figure

Fully-Binarized, Parallel, RRAM-based Computing Primitive for In-Memory Similarity Search

In this work, we propose a fully-binarized XOR-based IMSS (In-Memory Similarity Search) using RRAM (Resistive Random Access Memory) arrays. XOR (Exclusive OR) operation is realized using 2T-2R bitcells arranged along the column in an array. This enables simultaneous match operation across multiple stored data vectors by performing analog column-wise XOR operation and summation to compute HD (Hamming Distance). The proposed scheme is experimentally validated on fabricated RRAM arrays. Full-system validation is performed through SPICE simulations using open source Skywater 130 nm CMOS PDK demonstrating energy of 17 fJ per XOR operation using the proposed bitcell with a full-system power dissipation of 145 $\mu$W. Using projected estimations at advanced nodes (28 nm) energy savings of $\approx$1.5$\times$ compared to the state-of-the-art can be observed for a fixed workload. Application-level validation is performed on HSI (Hyper-Spectral Image) pixel classification task using the Salinas dataset demonstrating an accuracy of 90%

Resistive Switching Device Technology Based on Silicon Oxide for Improved ON-OFF Ratio--Part II: Select Devices

The cross-point architecture for memory arrays is widely considered as one of the most attractive solutions for storage and memory circuits thanks to simplicity, scalability, small cell size, and consequently high density and low cost. Cost-scalable vertical 3-D cross-point architectures, in particular, offer the opportunity to challenge Flash memory with comparable density and cost. To develop scalable cross-point arrays, however, select devices with sufficient ON-OFF ratio, current capability, and endurance must be available. This paper presents a select device technology based on volatile resistive switching with Cu and Ag top electrode and silicon oxide (SiOₓ) switching materials. The select device displays ultrahigh resistance window and good current capability exceeding 2 MAcm⁻². Retention study shows a stochastic voltage-dependent ON-OFF transition time in the 10 μs-1 ms range, which needs to be further optimized for fast memory operation in storage class memory arrays

SiOx-based resistive switching memory (RRAM) for crossbar storage/select elements with high on/off ratio

Resistive switching memory (RRAM) is among the most promising technologies for storage class memory (SCM) and embedded nonvolatile memory (eNVM). Feasibility of RRAM as SCM and/or embedded memory requires large on/off ratio, good endurance, high retention, and the availability of a robust select element for crossbar array integration. This work presents Ti/SiOx RRAM with high on/off ratio (>104), good endurance (>107), high uniformity and strong retention (260°C for 1 hour), thanks to the high SiOx band gap. Ag/SiOx devices show volatile switching with high on/off ratio (> 107) and bidirectional operation applicable to select devices in crossbar arrays