The impact of traffic localisation on the performance of NoCs for very large manycore systems

The scaling of semiconductor technologies is leading to processors with increasing numbers of cores. The adoption of Networks-on-Chip (NoC) in manycore systems requires a shift in focus from computation to communication, as communication is fast becoming the dominant factor in processor performance. In large manycore systems, performance is predicated on the locality of communication. In this work, we investigate the performance of three NoC topologies for systems with thousands of processor cores under two types of localised traffic. We present latency and throughput results comparing fat quadtree, concentrated mesh and mesh topologies under different degrees of localisation. Our results, based on the ITRS physical data for 2023, show that the type and degree of localisation of traffic significantly affects the NoC performance, and that scale-invariant topologies perform worse than flat topologies

Shortest path routing algorithm for hierarchical interconnection network-on-chip

Interconnection networks play a significant role in efficient on-chip communication for multicore systems. This paper introduces a new interconnection topology called the Hierarchical Cross Connected Recursive network (HCCR) and a shortest path routing algorithm for the HCCR. Proposed topology offers a high degree of regularity, scalability, and symmetry with a reduced number of links and node degree. A unique address encoding scheme is proposed for hierarchical graphical representation of HCCR networks, and based on this scheme a shortest path routing algorithm is devised. The algorithm requires 5(k-1) time where k=logn4-2 and k>0, in worst case to determine the next node along the shortest path

Framework for handling data veracity in big data

Big Data is the term used for massive amount of data collected by different means and in various formats. Data Veracity refers to the uncertainty of available data; this means that the quality of the collected data cannot be trusted. This paper reports on ongoing research based on using the Semantic Web technology to verify user entered data and increase dependability on Big Data. Validating, cleaning and reducing collected data are the major activities required to enhance the quality of the collected data

Metadata Extraction in Database Testing

The need for an automated testing tool to test the correctness of the database applications is crucial in our current day since databases play an important role in almost all organizations. Also, database’s behavior need to be verified in order to avoid costly errors and false information being extracted from them. The main aim of this paper was to create a component-based tester called DBSoft that tests the correctness of database application systems. The DBSoft toolkit consists of five tools as follows: information collection with the Parser tool, test case generation with the Input Generator tool, test case implementation with the Output Generator tool, test case validation with the Output Validator tool and report generation with the Report Generator tool

TESTABILITY OF INFORMATION LEAK IN THE SOURCE CODE FOR INDEPENDENT TEST ORGANIZATION BY USING BACK PROPAGATION ALGORITHM

A strategy for software testing integrates the design of software test cases into a wellplanned series of steps that results in a successful development of the software security. The strategy provides the secure source code test by Independent Test Organization (ITO) that describes the steps to be taken, when, and how much effort, time, and resources will be required. The strategy incorporates test planning, test case design, test execution, test result collection and test leak information and evaluation. In this work we speak about the testability of leak information in source code and how to detect and protect it inside the ITO. In this paper we present a privacy preserving algorithm for the neural network learning to detect and protect the leak information in source code between two parties the programmer (source code) and Independent Test Organization (Sensor). We show that our algorithm is very secure and the sensor inside Independent Test Organization is able to detect and protect all leaks information inside the source code. We demonstrate the efficiency of our algorithm by experiments on real world data. We present new technology for software Security using Back Propagation algorithm. That is embedded sensor to analyze the source code inside the ITO. By using embedded sensor we can detect and protect in real time all the attacks or leaks of information inside the source code. The connection between an Artificial Neural Networks and source code analysis inside Independent Test Organization is providing a great help for the software security

Analysis of the estimationof efficiency and safety of hypnotic drugs in elderly patients

Given the widespread use of hypnotics drugs to normalize sleep and the prevalence in the target group of elderly patients we have studied the spectrum of pharmacological safety of this group of drugs in geriatric patients

Extracting student patterns from log file Moodle course: A case study

This paper introduces a set of extracted factors from Moodle log file of the selected course as a case study that aims to capture student Engagement (E), Behavior (B), Personality (Pers) and Performance (P). The factors are applied to identify students’ EBPersP with different course activities. The data set used in this paper was selected from the "Introduction to Computer Science" online course that captures 273,906 records as a log file for 29 students, delivered in Spring 2020. The paper also tries to show whether there is a relationship between student engagement, behavior and personality and their performance. Results show different patterns of students’ interactions with course contents, activities, and assessments. Specifically, our findings highlight that students' EBPersP could be extracted from Moodle log files. In addition, the extracted factors could assist instructors on how to focus more on students with low and average performance, giving them more attention to enhancing their performance.

Advanced management techniques for many-core communication systems

The way computer processors are built is changing. Nowadays, computer processor performance is increased by adding more processing cores on a single chip instead of making processors larger and faster. The traditional approach is no longer viable, due to limits in transistor scaling. Both industry and academia agree that scaling the number of processing cores to hundreds or thousands on a single chip is the only way to scale computer processor performance from now on. Consequently, the performance of these future many-core systems with thousands of cores will heavily depend on the Network-on-Chip (NoC) architecture to provide scalable communication. Therefore, as the number of cores increases the locality will only become more important. Communication locality is essential to reduce latency and increase performance. Many-core systems should be designed such that cores communicate mainly to the neighbouring cores, in order to minimise the communication cost. We investigate the network performance of different topologies using the ITRS physical data for the year 2023. For this reason, we propose abstract synthetic traffic generation models to explore the locality behaviour in many-core NoC systems. Using the synthetic traffic models - group clustering model and ring clustering model - traffic distance metrics may be adjusted with locality parameters. We choose two many-core NoC architectures - distributed memory architecture and shared memory architecture - to examine whether enforcing locality on different architectures may have a diverse effect on the network performance of different topologies. Distributed memory architecture uses the message passing method of communication to communicate between cores. Our results show that the degree of locality and the clustering model strongly affect the performance of the network. Scale-invariant topologies, such as the fat quadtree, perform worse than flat ones because the reduced hop count is outweighed by the longer wire delays. In shared memory architecture, threads communicate with each other by storing data in shared cache lines. We design a hierarchical cache model that benefits from communication locality because many-core cache hierarchy that fails to exploit locality may end up having more cores delayed, thereby decreasing the network performance. Our results show that the locality model of thread placement and the distance of placing them significantly affect the NoC performance. Furthermore, they show that scale-invariant topologies perform better than flat topologies. Then, we demonstrate that implementing directory-based cache coherency has only a small overhead on the cache size. Using cache coherency protocol in our proposed hierarchical cache model, we show that network performance decreases only slightly. Hence, cache coherency scales, and it is possible to have shared memory architecture with thousands of cores

Evaluation of the Memory Communication Traffic in a Hierarchical Cache Model for Massively-Manycore Processors

The scaling of semiconductor technologies is leading to processors with increasing numbers of cores. A key enabler in manycore systems is the use of Networks-on-Chip (NoC) as a global communication mechanism. The adoption of NoCs in manycore systems requires a shift in focus from computation to communication, as communication is fast becoming the dominant factor in processor performance. Many researchers have focused on direct communication between cores in the NoC, however in a manycore processor the communication is actually between the cores and the memory hierarchy. In this work, we investigate the memory communication traffic of shared threads in a hierarchical cache architecture. We argue that the performance scalability for shared-memory applications in a hierarchical cache architecture for systems with thousands of processor cores depends on the distance between threads sharing memory in terms of the cache hierarchy (the "memory distance"). We present latency and throughput results comparing fat quadtree, concentrated mesh and mesh topologies as a function of the "memory distance" between the threads. Our results using the ITRS physical data for 2023 show that the model of thread placement and the distance of placing them significantly affects the NoC performance, and that scale-invariant topologies perform better than flat topologies

A Guidance Based Approach for Enhancing the e-Government Interoperability

Developing e-Government interoperability in the government context is a complex task. As interoperability in government context is associated and hindered by many challenges and barriers connected to government nature of complexity. Interoperability is generally defined as the ability for two (or more) systems to exchange information and to use the information that has been exchanged. In this paper, we focus on computing systems interoperability across government ministries to achieve interoperable e-Government IT based solutions. In order to achieve e-Government interoperability in an organised and efficient way, this paper establishes a guidance-based approach for enhancing the e-Government Interoperability. This contribution is motivated by the limitations of the traditional software engineering methodologies in terms of analysis, design and development frameworks to a point that they can hardly cope with the growing issues of e-Government services interoperability