Emulating and evaluating hybrid memory for managed languages on NUMA hardware

Non-volatile memory (NVM) has the potential to become a mainstream memory technology and challenge DRAM. Researchers evaluating the speed, endurance, and abstractions of hybrid memories with DRAM and NVM typically use simulation, making it easy to evaluate the impact of different hardware technologies and parameters. Simulation is, however, extremely slow, limiting the applications and datasets in the evaluation. Simulation also precludes critical workloads, especially those written in managed languages such as Java and C#. Good methodology embraces a variety of techniques for evaluating new ideas, expanding the experimental scope, and uncovering new insights. This paper introduces a platform to emulate hybrid memory for managed languages using commodity NUMA servers. Emulation complements simulation but offers richer software experimentation. We use a thread-local socket to emulate DRAM and a remote socket to emulate NVM. We use standard C library routines to allocate heap memory on the DRAM and NVM sockets for use with explicit memory management or garbage collection. We evaluate the emulator using various configurations of write-rationing garbage collectors that improve NVM lifetimes by limiting writes to NVM, using 15 applications and various datasets and workload configurations. We show emulation and simulation confirm each other's trends in terms of writes to NVM for different software configurations, increasing our confidence in predicting future system effects. Emulation brings novel insights, such as the non-linear effects of multi-programmed workloads on NVM writes, and that Java applications write significantly more than their C++ equivalents. We make our software infrastructure publicly available to advance the evaluation of novel memory management schemes on hybrid memories

RPPM : Rapid Performance Prediction of Multithreaded workloads on multicore processors

Analytical performance modeling is a useful complement to detailed cycle-level simulation to quickly explore the design space in an early design stage. Mechanistic analytical modeling is particularly interesting as it provides deep insight and does not require expensive offline profiling as empirical modeling. Previous work in mechanistic analytical modeling, unfortunately, is limited to single-threaded applications running on single-core processors. This work proposes RPPM, a mechanistic analytical performance model for multi-threaded applications on multicore hardware. RPPM collects microarchitecture-independent characteristics of a multi-threaded workload to predict performance on a previously unseen multicore architecture. The profile needs to be collected only once to predict a range of processor architectures. We evaluate RPPM's accuracy against simulation and report a performance prediction error of 11.2% on average (23% max). We demonstrate RPPM's usefulness for conducting design space exploration experiments as well as for analyzing parallel application performance

Fairness-aware scheduling on single-ISA heterogeneous multi-cores

Single-ISA heterogeneous multi-cores consisting of small (e.g., in-order) and big (e.g., out-of-order) cores dramatically improve energy- and power-efficiency by scheduling workloads on the most appropriate core type. A significant body of recent work has focused on improving system throughput through scheduling. However, none of the prior work has looked into fairness. Yet, guaranteeing that all threads make equal progress on heterogeneous multi-cores is of utmost importance for both multi-threaded and multi-program workloads to improve performance and quality-of-service. Furthermore, modern operating systems affinitize workloads to cores (pinned scheduling) which dramatically affects fairness on heterogeneous multi-cores. In this paper, we propose fairness-aware scheduling for single-ISA heterogeneous multi-cores, and explore two flavors for doing so. Equal-time scheduling runs each thread or workload on each core type for an equal fraction of the time, whereas equal-progress scheduling strives at getting equal amounts of work done on each core type. Our experimental results demonstrate an average 14% (and up to 25%) performance improvement over pinned scheduling through fairness-aware scheduling for homogeneous multi-threaded workloads; equal-progress scheduling improves performance by 32% on average for heterogeneous multi-threaded workloads. Further, we report dramatic improvements in fairness over prior scheduling proposals for multi-program workloads, while achieving system throughput comparable to throughput-optimized scheduling, and an average 21% improvement in throughput over pinned scheduling

Crystal gazer : profile-driven write-rationing garbage collection for hybrid memories

Non-volatile memories (NVM) offer greater capacity than DRAM but suffer from high latency and low write endurance. Hybrid memories combine DRAM and NVM to form scalable memory systems with the promise of high capacity, low energy consumption, and high endurance. Automatically managing hybrid NVM-DRAM memories to achieve their promise without changing user applications or their programming models remains an open question. This paper uses garbage collection in managed languages to exploit NVM capacity while preventing NVM wear out in hybrid memories with no changes to the programming model. We introduce profile-driven write-rationing garbage collection. Allocation sites that produce frequently written objects are predicted based on previous program executions. Objects are initially allocated in a DRAM nursery space. The collector copies surviving nursery objects from highly written sites to a mature DRAM space and read-mostly objects to a mature NVM space.Write-intensity prediction for 15 Java benchmarks accurately places objects in the correct space, eliminating expensive object monitoring from prior write-rationing garbage collectors. Furthermore, our technique exposes a Pareto tradeoff between DRAM usage and NVM lifetime, unlike prior work. Experimental results on NUMA hardware that emulates hybrid NVM-DRAM memory demonstrates that profile-driven write-rationing garbage collection reduces the number of writes to NVM compared to prior work to extend its lifetime, maximizes the use of NVM for its capacity, and achieves good performance

RPPM : rapid performance prediction of multithreaded applications on multicore hardware

This paper proposes RPPM which, based on a microarchitecture-independent profile of a multithreaded application, predicts its performance on a previously unseen multicore platform. RPPM breaks up multithreaded program execution into epochs based on synchronization primitives, and then predicts per-epoch active execution times for each thread and synchronization overhead to arrive at a prediction for overall application performance. RPPM predicts performance within 12 percent on average (27 percent max error) compared to cycle-level simulation. We present a case study to illustrate that RPPM can be used for making accurate multicore design trade-offs early in the design cycle

Formulation and characterization of a multiple emulsion containing 1% L-ascorbic acid

The purpose of the study was to prepare a stable multiple emulsion containing a skin anti-aging agent and using paraffin oil. Vitamin C, was incorporated into the inner aqueous phase of water-in-oil-in-water (w/o/w) multiple emulsion at a concentration of 1%. Multiple emulsion was prepared by two step method. Stability studies were performed at different accelerated conditions, i.e. 8 oC (in refrigerator), 25 oC (in oven), 40 oC (in oven), and 40 oC at 75% RH (in stability cabin) for 28 days to predict the stability of formulations. Different parameters, namely pH, globule size, electrical conductivity and effect of centrifugation (simulating gravity) were determined during stability studies. Data obtained was evaluated statistically using ANOVA two way analyses and LSD tests. Multiple emulsion formulated was found to be stable at lower temperatures (i.e. 8 and 25 oC) for 28 days. No phase separation was observed in the samples during stability testing. It was found that there was no significant change (p > 0.05) in globule sizes in most of the samples kept at various conditions. Insignificant changes (p > 0.05) in both pH and conductivity values were determined for the samples kept at 8, 40, and 40 oC at 75% RH, throughout the study period. Further studies are needed to formulate more stable emulsions with other emulsifying agents. KEY WORDS: Multiple emulsion, Vitamin C, StabilityBull. Chem. Soc. Ethiop. 2010, 24(1), 1-10.

Design and development of a multi-functional bi-anisotropic metasurface with ultra-wide out of band transmission

This paper presents a multi-functional bi-anisotropic metasurface having ultra-wide out of band transmission characteristics. The proposed metasurface is comprised of 90° rotated T-shaped configuration yielding greater than or equal to 50% out-of-band transmission from above L- to X-band. Moreover, this metasurface achieves a maximum of 99% out-of-band transmission at lower frequency bands (i.e., L-band). The simultaneous absorptive and controlled reflection functionalities are achieved at 15.028 to 15.164 GHz along with polarization-insensitive and angular stable properties. The proposed metasurface yields state-of-the-art features compared to already published papers and has broader scope for Fabry Perot cavity, Radar cross-section (RCS) reduction, electromagnetic compatibility and interference (EMC/I) shielding, selective multi-frequency bolometers, ultrathin wave trapping filters, sensors and beam-splitters in the microwave domain