An x-band RFIC active phase shifter

Abstract— An active RFIC X-band phase shifter is implemented using IHP SiGe HBT 0.25 μm SGB25V technology with an improved vector sum method. The chip is formed by a three way Wilkinson power divider, three phase delays for 0-120-240 degrees, three similar RFIC LNAs and a final three way Wilkinson power combiner on the same chip and occupies an area of 4x1.8 mm2. The circuit provides both phase and amplitude control without the need of any additional digital circuitry. Phase shifting is simply based on the weighted vector sum of three vectors which are separated by 120º from each other. All 0-360 degree phase can be scanned simply by this method with the addition of amplitude control. The RFIC LNA circuit is fabricated and measurement results show that LNA has a gain of 10 - 13 dB with in the band of 6-9 GHz and 2-3 dB NF within the same band. The simulation results show that the phase can be scanned from 0-360 degrees with average 7 degree resolution for a 2 dB amplifier gain change. The gain of the overall active phase shifter circuit is 12-13 dB with output gain flatness is 1 dB and the circuit consumes 15.36 mW power. The circuit combines the amplifier with phase shifter and can be used for X-band applications

Design and fabrication of A Ku-band low noise amplifier using FR-4 substrate

The low noise amplifier (LNA) plays an important role in many communication systems, especially at the receiver’s front-ends. In modern RF designs, The LNA is usually fabricated on a microstrip printed circuit board (PCB) due to its simplicity and ability of integrating flexibly with other components in a receiving circuitry unit. At frequencies lower than 6 GHz, the most prevalent substrate material for a microstrip LNA is FR-4 while at higher frequencies of over 10 GHz, it is challenging to design the LNA using this material without causing considerable losses to the RF signal. There are many works related to design microstrip LNA at high frequencies, however, the dielectric substrates used in most of them were high-cost materials for low dielectric loss. This paper introduces an LNA topology using the common, low-cost FR-4 substrate which can be operated in Ku-band for applications such as small satellites’ receivers, with the expected noise figure of lower than 1 dB, gain of around 10 dB and the return loss of around -10 dB. The stepped impedance matching technique has been used for transmission line optimization. The simulated and measured results are presented

Advanced space communications architecture study. Volume 2: Technical report

The technical feasibility and economic viability of satellite system architectures that are suitable for customer premise service (CPS) communications are investigated. System evaluation is performed at 30/20 GHz (Ka-band); however, the system architectures examined are equally applicable to 14/11 GHz (Ku-band). Emphasis is placed on systems that permit low-cost user terminals. Frequency division multiple access (FDMA) is used on the uplink, with typically 10,000 simultaneous accesses per satellite, each of 64 kbps. Bulk demodulators onboard the satellite, in combination with a baseband multiplexer, convert the many narrowband uplink signals into a small number of wideband data streams for downlink transmission. Single-hop network interconnectivity is accomplished via downlink scanning beams. Each satellite is estimated to weigh 5600 lb and consume 6850W of power; the corresponding payload totals are 1000 lb and 5000 W. Nonrecurring satellite cost is estimated at $110 million, with the first-unit cost at$113 million. In large quantities, the user terminal cost estimate is $25,000. For an assumed traffic profile, the required system revenue has been computed as a function of the internal rate of return (IRR) on invested capital. The equivalent user charge per-minute of 64-kbps channel service has also been determined

Bidirectional common-path for 8-to-24 gHz low noise SiGe BiCMOS T/R module core-chip

This thesis is based on the design of an 8-to-24 GHz low noise SiGe BiCMOS Transmitter/Receiver (T/R) Module core-chip in a small area by bidirectional common-path. The next-generation phased array systems require multi-functionality and multi-band operation to form multi-purpose integrated circuits. Wide bandwidth becomes a requirement for the system in various applications, such as electronic warfare, due to leading cheaper and lighter system solutions. Although III-V technologies can satisfy the high-frequency specifications, they are expensive and have a large area. The silicon-based technologies promise high integration capability with low cost, but they sacrifice from the performance to result in desired bandwidth. The presented dissertation targets system and circuit level solutions on the described content. The wideband core-chip utilized a bidirectional common path to surpass the bandwidth limitations. The bidirectionality enhances the bandwidth, noise, gain and area of the transceiver by the removal of the repetitive blocks in the unidirectional common chain. This approach allows succeeding desired bandwidth and compactness without sacrificing from the other high-frequency parameters. The realized core-chip has 31.5 and 32 dB midband gain for the receiver and transmitter respectively, with a + 2.1 dB /GHz of positive slope. Its RMS phase and amplitude errors are lower than 5.60 and 0.8 dB, respectively for 4-bit of resolution. The receiver noise figure is lower than 5 dB for the defined bandwidth while dissipating 112 mW of power in a 5.5 mm2 area. The presented results verify the advantage of the favored architecture and might replace the III-V based counterparts

Design of a Magnetically Tunable Low Noise Amplifier in 0.13 um CMOS Technology

With legacy technologies present and approaching new wireless standards, the 1-10 GHz band of frequencies is quickly becoming saturated. Although saturated, the frequency bands are being utilized inefficiently. Cognitive radio, an intelligent wireless communication system, is the novel solution for the efficient utilization of the frequency bands. Front-end receivers for cognitive radio will need the capability to receive and process multiple frequency bands and a key component is the low noise amplifier (LNA). A tunable LNA using a new magnetically tuned input impedance matching network is presented. The LNA has been designed and simulated in a commercially available 0.13 μm CMOS technology and is capable of tuning from 3.2 GHz to 4.6 GHz as S11 \u3c -10 dB. Within this bandwidth the maximum power gain is 16.2 dB, the maximum noise figure is 7.5 dB, and the minimum IIP3 is -6.4 dBm. The total power consumption of the LNA (neglecting the buffer required to drive the 50 Ω test equipment) is 50 mW. This tunable LNA introduces a new magnetically tunable matching technique and tuning scheme capable of continuous frequency variation for LNAs. It is expected that this technique could be expanded to realize LNAs with a tunable, narrow-band response that can cover the entire 1-10 GHz band of frequencies. The presented tunable LNA has demonstrated the capability to cover and process multiple frequencies and can be used for reconfigurable systems. A tunable LNA design is the first step in an effort to realize a fully reconfigurable front-end radio frequency (RF) receiver for future cognitive radio applications

Towards an optimal trade-off of functional requirements against size, power and cost for phased array asics

Abstract – In this paper, we investigate various technologies and trade-offs used for manufacturing of integrated circuits with respect to their performance characteristics such as RF frequency, gain, noise figure, linearity and power consumption. This investigation is crucial for design of transceivers at microwave and higher frequencies. In the following, we show the in-house designed prototype of a highly integrated X- and Ku-band planar phased array receiver, having 8 channels and 64 antenna elements based on this investigation. The die size of the 8-channel phased array receiver with 2 GHz IF-bandwidth is 4 mm × 3.8 mm and the size of the prototype is 11 cm × 9.5 c

Design of Ka-Band Low Noise Amplifier Using CMOS Technology

In this paper, design of a Low Noise Amplifier is undertaken for higher frequency bands, particularly Ka-band. The designed LNA can be used in satellite transponders for the mentioned frequency band. Generally LNAs are the first block in a transponder and are very sophisticated in trems of noise performance. A common-source topology along with source degeneration is used to achieve low noise figure and linearity with high gain. The use of CMOS technology provides new applications in designing this amplifier. It offers designs at lower cost, reduced power consumption and higher levels of integration. Proposed circuit achieves a maximum gain of 23dB with a relatively low noise figure of 2.9dB. This system can work in Deep-Space region as part of a satellite transponder