Within-Die Delay Variation Measurement And Analysis For Emerging Technologies Using An Embedded Test Structure

Both random and systematic within-die process variations (PV) are growing more severe with shrinking geometries and increasing die size. Escalation in the variations in delay and power with reductions in feature size places higher demands on the accuracy of variation models. Their availability can be used to improve yield, and the corresponding profitability and product quality of the fabricated integrated circuits (ICs). Sources of within-die variations include optical source limitations, and layout-based systematic effects (pitch, line-width variability, and microscopic etch loading). Unfortunately, accurate models of within-die PVs are becoming more difficult to derive because of their increasingly sensitivity to design-context. Embedded test structures (ETS) continue to play an important role in the development of models of PVs and as a mechanism to improve correlations between hardware and models. Variations in path delays are increasing with scaling, and are increasingly affected by neighborhood\u27 interactions. In order to fully characterize within-die variations, delays must be measured in the context of actual core-logic macros. Doing so requires the use of an embedded test structure, as opposed to traditional scribe line test structures such as ring oscillators (RO). Accurate measurements of within-die variations can be used, e.g., to better tune models to actual hardware (model-to-hardware correlations). In this research project, I propose an embedded test structure called REBEL (Regional dELay BEhavior) that is designed to measure path delays in a minimally invasive fashion; and its architecture measures the path delays more accurately. Design for manufacture-ability (DFM) analysis is done on the on 90 nm ASIC chips and 28nm Zynq 7000 series FPGA boards. I present ASIC results on within-die path delay variations in a floating-point unit (FPU) fabricated in IBM\u27s 90 nm technology, with 5 pipeline stages, used as a test vehicle in chip experiments carried out at nine different temperature/voltage (TV) corners. Also experimental data has been analyzed for path delay variations in short vs long paths. FPGA results on within-die variation and die-to-die variations on Advanced Encryption System (AES) using single pipelined stage are also presented. Other analysis that have been performed on the calibrated path delays are Flip Flop propagation delays for both rising and falling edge (tpHL and tpLH), uncertainty analysis, path distribution analysis, short versus long path variations and mid-length path within-die variation. I also analyze the impact on delay when the chips are subjected to industrial-level temperature and voltage variations. From the experimental results, it has been established that the proposed REBEL provides capabilities similar to an off-chip logic analyzer, i.e., it is able to capture the temporal behavior of the signal over time, including any static and dynamic hazards that may occur on the tested path. The ASIC results further show that path delays are correlated to the launch-capture (LC) interval used to time them. Therefore, calibration as proposed in this work must be carried out in order to obtain an accurate analysis of within-die variations. Results on ASIC chips show that short paths can vary up to 35% on average, while long paths vary up to 20% at nominal temperature and voltage. A similar trend occurs for within-die variations of mid-length paths where magnitudes reduced to 20% and 5%, respectively. The magnitude of delay variations in both these analyses increase as temperature and voltage are changed to increase performance. The high level of within-die delay variations are undesirable from a design perspective, but they represent a rich source of entropy for applications that make use of \u27secrets\u27 such as authentication, hardware metering and encryption. Physical unclonable functions (PUFs) are a class of primitives that leverage within-die-variations as a means of generating random bit strings for these types of applications, including hardware security and trust. Zynq FPGAs Die-to-Die and within-die variation study shows that on average there is 5% of within-Die variation and the range of die-to-Die variation can go upto 3ns. The die-to-Die variations can be explored in much further detail to study the variations spatial dependance. Additionally, I also carried out research in the area data mining to cater for big data by focusing the work on decision tree classification (DTC) to speed-up the classification step in hardware implementation. For this purpose, I devised a pipelined architecture for the implementation of axis parallel binary decision tree classification for meeting up with the requirements of execution time and minimal resource usage in terms of area. The motivation for this work is that analyzing larger data-sets have created abundant opportunities for algorithmic and architectural developments, and data-mining innovations, thus creating a great demand for faster execution of these algorithms, leading towards improving execution time and resource utilization. Decision trees (DT) have since been implemented in software programs. Though, the software implementation of DTC is highly accurate, the execution times and the resource utilization still require improvement to meet the computational demands in the ever growing industry. On the other hand, hardware implementation of DT has not been thoroughly investigated or reported in detail. Therefore, I propose a hardware acceleration of pipelined architecture that incorporates the parallel approach in acquiring the data by having parallel engines working on different partitions of data independently. Also, each engine is processing the data in a pipelined fashion to utilize the resources more efficiently and reduce the time for processing all the data records/tuples. Experimental results show that our proposed hardware acceleration of classification algorithms has increased throughput, by reducing the number of clock cycles required to process the data and generate the results, and it requires minimal resources hence it is area efficient. This architecture also enables algorithms to scale with increasingly large and complex data sets. We developed the DTC algorithm in detail and explored techniques for adapting it to a hardware implementation successfully. This system is 3.5 times faster than the existing hardware implementation of classification.\u2

High-precision fluorescence photometry for real-time biomarkers detection

Les derniers évènements planétaires et plus particulièrement l'avènement sans précédent du nouveau coronavirus augmente la demande pour des appareils de test à proximité du patient. Ceux-ci fonctionnent avec une batterie et peuvent identifier rapidement des biomarqueurs cibles. Pareils systèmes permettent aux utilisateurs, disposant de connaissances limitées en la matière, de réagir rapidement, par exemple dans la détection d'un cas positif de COVID-19. La mise en œuvre de l'élaboration d'un tel instrument est un projet multidisciplinaire impliquant notamment la conception de circuits intégrés, la programmation, la conception optique et la biologie, demandant tous une maîtrise pointue des détails. De plus, l'établissement des spécifications et des exigences pour mesurer avec précision les interactions lumière-échantillon s'additionnent au besoin d'expérience dans la conception et la fabrication de tels systèmes microélectriques personnalisés et nécessitent en elles-mêmes, une connaissance approfondie de la physique et des mathématiques. Ce projet vise donc à concevoir et à mettre en œuvre un appareil sans fil pour détecter rapidement des biomarqueurs impliqués dans des maladies infectieuses telles que le COVID-19 ou des types de cancers en milieu ambulatoire. Cette détection se fait grâce à des méthodes basées sur la fluorescence. La spectrophotométrie de fluorescence permet aux médecins d'identifier la présence de matériel génétique viral ou bactérien tel que l'ADN ou l'ARN et de les caractériser. Les appareils de paillasse sont énormes et gourmand énergétiquement tandis que les spectrophotomètres à fluorescence miniatuarisés disponibles dans le commerce sont confrontés à de nombreux défis. Ces appareils miniaturisés ont été découverts en tirant parti des diodes électroluminescentes (DEL) à semi-conducteurs peu coûteuses et de la technologie des circuits intégrés. Ces avantages aident les scientifiques à réduire les erreurs possibles, la consommation d'énergie et le coût du produit final utilisé par la population. Cependant, comme leurs homologues de paillasse, ces appareils POC doivent quantifier les concentrations en micro-volume d'analytes sur une large gamme de longueurs d'onde suivant le cadre d'une économie en ressources. Le microsystème envisagé bénéficie d'une approche de haute précision pour fabriquer une puce microélectronique CMOS. Ce procédé se fait de concert avec un boîtier personnalisé imprimé en 3D pour réaliser le spectrophotomètre à la fluorescence nécessaire à la détection quantitative d'analytes en microvolume. En ce qui a trait à la conception de circuits, une nouvelle technique de mise à auto-zeroing est appliquée à l'amplificateur central, celui-ci étant linéarisé avec des techniques de recyclage et de polarisation adaptative. Cet amplificateur central est entièrement différentiel et est utilisé dans un amplificateur à verrouillage pour récupérer le signal d'intérêt éclipsé par le bruit. De plus, l'augmentation de la sensibilité de l'appareil permet des mesures quantitatives avec des concentrations en micro-volume d'analytes ayant moins d'erreurs de prédiction de concentration. Cet avantage cumulé à une faible consommation d'énergie, un faible coût, de petites dimensions et un poids léger font de notre appareil une solution POC prometteuse dans le domaine de la spectrophotométrie de fluorescence. La validation de ce projet s'est fait en concevant, fabriquant et testant un prototype discret et sans fil. Son article de référence a été publié dans IEEE LSC 2018. Quant à la caractérisation et l'interprétation du prototype d'expériences in vitro à l'aide d'une interface MATLAB personnalisée, cet article a été publié dans IEEE Sensors journal (2021). Les circuits intégrés et les photodétecteurs ont été fabriqués ont été conçus et fabriqués par Cadence en 2019. Relativement aux solutions de circuit proposées, elles ont été fabriquées avec la technologie CMOS 180 nm et publiées lors de la conférence IEEE MWSCAS 2020. Tout comme cette dernière contribution, les expériences in vitro avec le dispositif proposé incluant la puce personnalisée et le boîtier imprimé en 3D ont été réalisés et les résultats électriques et optiques ont été soumis au IEEE Journal of Solid-State Circuits (JSSC 2022).The most recent and unprecedented experience of the novel coronavirus increases the demand for battery-operated near-patient testing devices that can rapidly identify the target biomarkers. Such systems enable end-users with limited resources to quickly get feedback on various medical tests, such as detecting positive COVID-19 cases. Implementing such a device is a multidisciplinary project dealing with multiple areas of expertise, including integrated circuit design, programming, optical design, and biology, each of which needs a firm grasp of details. Alongside the need for experience in designing and manufacturing custom microelectronic systems, establishing the specifications and requirements to precisely measure the light-sample interactions requires an in-depth knowledge of physics and mathematics. This project aims to design and implement a wireless point-of-care (POC) device to rapidly detect biomarkers involved in infectious diseases such as COVID-19 or different types of cancers in an ambulatory setting using fluorescence-based methods. Fluorescence spectrophotometry allows physicians to identify and characterize viral or bacterial genetic materials such as DNAs or RNAs. The benchtop devices that are currently available are bulky and power-hungry, whereas the commercially available miniaturized fluorescence spectrophotometers are facing many challenges. Many of these difficulties have been resolved in literature thanks to inexpensive semiconductor light-emitting diodes (LEDs) and integrated circuits technology. Such advantages aid scientists in decreasing the size, power consumption, and cost of the final product for end-users. However, like the benchtop counterparts, such POC devices must quantify micro-volume concentrations of analytes across a wide wave length range under an economy of resources. The envisioned microsystem benefits from a high-precision approach to fabricating a CMOS microelectronic chip combined with a custom 3D-printed housing. This implementation results in a fluorescence spectrophotometer for qualitative and quantitative detection of micro-volume analytes. In terms of circuit design, a novel switched-biasing ping-pong auto-zeroed technique is applied to the core amplifier, linearized with recycling and adaptive biasing techniques. The fully differential core amplifier is utilized within a lock-in amplifier to retrieve the signal of interest overshadowed by noise. Increasing the device's sensitivity allows quantitative measurements down to micro-volume concentrations of analytes with less concentration prediction error. Such an advantage, along with low-power consumption, low cost, low weight, and small dimensions, make our device a promising POC solution in the fluorescence spectrophotometry area. The approach of this project was validated by designing, fabricating, and testing a discrete and wireless prototype. Its conference paper was published in IEEE LSC 2018, and the prototype characterization and interpretation of in vitro experiments using a custom MATLAB interface were published in IEEE Sensors Journal (2021). The integrated circuits and photodetectors were designed and fabricated by the Cadence circuit design toolbox (2019). The proposed circuit solutions were fabricated with 180-nm CMOS technology and published at IEEE MWSCAS 2020 conference. As the last contribution, the in vitro experiments with the proposed device, including the custom chip and 3D-printed housing, were performed, and the electrical and optical results were submitted to the IEEE Journal of Solid-State Circuits (JSSC 2022)

Identifying and evaluating aging signatures in light emitting diode lighting systems

Dans ce travail, les dégradations des diodes électroluminescentes (DEL) ont été étudiées en identifiant et en évaluant leurs signatures électriques et photométriques en vieillissement accéléré sous stress thermique et électrique. Un prototype de banc de test expérimental a été développé et construit spécifiquement pour cette étude ce qui nous a permis de tester 128 échantillons en appliquant différentes conditions de stress thermiques et électriques. Quatre types différents de DEL ont été étudié avec des caractéristiques techniques similaires (température de couleur, courant nominal, mono-puce,...) mais avec des technologies différentes couvrant les principaux acteurs du marché (Cree, Osram, Philips et Seoul Semiconductor). Les échantillons ont d'abord été caractérisés à leur état initial, puis soumis à des conditions de stress électrique (à 350mA ou 1050mA) et thermique (fixé à 50°C). Les mécanismes de défaillance ont été analysés en étudiant l'évolution des signatures électriques et photométriques. Ces caractérisations ont permis d'évaluer et de déterminer l'origine des dégradations à différents niveaux : puce semi-conductrice, interconnexions, phosphore ou encapsulation du dispositif. Les caractérisations électriques nous ont permis d'identifier les mécanismes de dégradation de la puce semi-conductrice et de déterminer la nature des dégradations au niveau du contact ohmique du dispositif (sous fort courant injecté). Les caractérisations photométriques complètent cette étude en évaluant les dégradations associées à l'optique (encapsulation et packaging).In this work, the degradation of light emitting diodes (LEDs) is studied by identifying and evaluating their aging signature during the stress time. The custom-made experimental test bench is built for realization of the test measurement. Through this experimental test bench, it allows to test a large amount of LED samples and enable to select different temperature condition and different current stress level. There are four different types of LED with similar characteristic in term of their color temperature, IF, VF, power (1W) and as monochip, but different technology coming from Cree, Osram, Philips and Seoul Semiconductor. The devices are firstly characterized their electrical and photometrical characteristic at their initial state, then they are submitted to different current stress condition at low current stress (350mA) and high current stress (1000mA) while the thermal stress is fixed at one temperature (50°C). The study of these devices failure mechanism is archived by using the primary method based on the electrical and photometrical characterization of the devices that allows to evaluate their degradation at different locations of the device components such as semiconductor chip, interconnection and device's package. The electrical characteristic of the device's I-V curve: at low injected current level and reverse bias allow us to identify the degradation characteristic of device's semiconductor chip, at high injected current level allows us to determine the degradation of device's ohmic contact and photometric characteristic allows us to evaluate the degradation of device's package system

Energy-efficient modulation and physical layer design for low terahertz band communication channel in 5G femtocell Internet of Things

© 2018 Elsevier B.V. High throughput capability of the terahertz band (0.3–10 THz) wireless communications is expected to be utilized by the fifth generation of mobile telecommunication systems and enable a plethora of new applications. Supporting devices will transfer large amounts of data in both directions, causing high energy consumption by the electronic circuitries of the equipment in use. Therefore, physical layer for these systems must be designed carefully in order to reduce energy consumption per bit. In this paper, the best performing modulation scheme and hardware parameters that minimize the energy consumption without affecting the system throughput are determined. THz band device technologies are outlined and a complete survey of the state-of-the-art low-THz band circuit blocks which are suitable for mass market production is given. It is shown that for short-range communications, M-ary quadrature amplitude modulation is the most energy-efficient technique that can lead up to 90% reduction in consumed energy. Moreover, optimal transceiver parameters which can be used to further minimize the energy consumption of the THz band system are examined

Resonance Ionization Mass Spectrometry of Calcium

This thesis describes the design and development of a new Resonance Ionization Mass Spectrometer instrument at the Dept, of Physics and Astronomy, the University of Glasgow, and some of the early laser spectroscopy and mass spectrometry investigations carried out with the instrument. The elemental trace analysis capability of the instrument has been measured to be better than 1ppm for both rubidium and calcium in complex matrices. Isotopic abundance ratios for calcium have been measured with an accuracy of +/-3% and with a precision of +/-5%. The laser ablation process has been investigated for a calcium metal sample for several ablation wavelengths. A good fit to data was obtained with a simple thermal process model. The laser ablation of calcium was observed to display a strong enhancement at a wavelength corresponding to a known two-photon resonant, one-photon ionization ("2+1") RIS scheme. The potential utility of this Resonant Laser Ablation process as an analytic technique is discussed. The laser ionization spectroscopy of calcium has been investigated over the wavelength region 413nm to 437nm. Two series of "2+1" transitions were observed, both displaying a strong ion yield enhancement in the vicinity of an intermediate resonace. Single photon, bound-bound transitions from excited states were also observed. The populating mechanisms and relative populations for these excited states have been investigated. A further series of observed lines has been assigned to two-photon resonant transitions from excited metastable states to autoionization levels, lying above the first ionization potential. Several spectral features have not yet been identified, possible mechanisms are discussed. A simple theoretical model for determining two-photon transition cross-sections is outlined. A population rate equation model has been developed to describe the dynamics of the resonance ionization process. These two theoretical models have been combined to generate theoretical ion yields for a "2+1" RIS scheme, a comparison with experimental data is presented. Mass spectra for a calcium metal sample have been obtained using several 'competing' analytic techniques: Laser Ionization Mass Analysis (LIMA) - Resonant Laser Ablation (RLA) - Non-resonant post-ionization of laser ablated neutrals (SALI) - Resonant post-ionization of laser ablated neutrals (RIMS) Significant differences in the observed selectivities, and consequent sensitivities, are discussed with regard to the analytic utility of each technique. The work on the laser spectroscopy and the mass spectrometry of calcium is solely that of the author