Efficient, High power Precision RF and mmWave Digital Transmitter Architectures

Digital transmitters offer several advantages over conventional analog transmitters such as reconfigurability, elimination of scaling-unfriendly, power hungry and bulky analog blocks and portability across technology. The rapid advancement of technology in CMOS processes also enables integration of complex digital signal processing circuitry on the same die as the digital transmitter to compensate for their non-idealities. The use of this digital assistance can, for instance, enable the use of highly efficient but nonlinear switching-class power amplifiers by compensating for their severe nonlinearity through digital predistortion. While this shift to digitally intensive transmitter architectures is propelled by the benefits stated above, several pressing challenges arise that vary in their nature depending on the frequency of operation - from RF to mmWave. Millimeter wave CMOS power amplifiers have traditionally been limited in output power due to the low breakdown voltage of scaled CMOS technologies and poor quality of on-chip passives. Moreover, high data-rates and efficient spectrum utilization demand highly linear power amplifiers with high efficiency under back-off. However, linearity and high efficiency are traditionally at odds with each other in conventional power amplifier design. In this dissertation, digital assistance is used to relax this trade-off and enable the use of state-of-the-art switching class power amplifiers. A novel digital transmitter architecture which simultaneously employs aggressive device-stacking and large-scale power combining for watt-class output power, dynamic load modulation for linearization, and improved efficiency under back-off by supply-switching and load modulation is presented. At RF frequencies, while the problem of watt-class power amplification has been long solved, more pressing challenges arise from the crowded spectrum in this regime. A major drawback of digital transmitters is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to RF and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in FDD systems due to receiver desensitization or impose stringent coexistence challenges. In this dissertation, new quantization noise suppression techniques are presented which, for the first time, contribute toward making watt-class fully-integrated digital RF transmitters a viable alternative for FDD and coexistence scenarios. Specifically, the techniques involve embedding a mixed-domain multi-tap FIR filter within highly-efficient watt-class switching power amplifiers to suppress quantization noise, enhancing the bandwidth of noise suppression, enabling tunable location of suppression and overcoming the limitations of purely digital-domain filtering techniques for quantization noise

Architectures and Integrated Circuits for Efficient, High-power "Digital'' Transmitters for Millimeter-wave Applications

This thesis presents architectures and integrated circuits for the implementation of energy-efficient, high-power "digital'' transmitters to realize high-speed long-haul links at millimeter-wave frequencies in nano-scale silicon-based processes

CMOS Data Converters for Closed-Loop mmWave Transmitters

With the increased amount of data consumed in mobile communication systems, new solutions for the infrastructure are needed. Massive multiple input multiple output (MIMO) is seen as a key enabler for providing this increased capacity. With the use of a large number of transmitters, the cost of each transmitter must be low. Closed-loop transmitters, featuring high-speed data converters is a promising option for achieving this reduced unit cost.In this thesis, both digital-to-analog (D/A) and analog-to-digital (A/D) converters suitable for wideband operation in millimeter wave (mmWave) massive MIMO transmitters are demonstrated. A 2 76 bit radio frequency digital-to-analog converter (RF-DAC)-based in-phase quadrature (IQ) modulator is demonstrated as a compact building block, that to a large extent realizes the transmit path in a closed-loop mmWave transmitter. The evaluation of an successive-approximation register (SAR) analog-to-digital converter (ADC) is also presented in this thesis. Methods for connecting simulated and measured performance has been studied in order to achieve a better understanding about the alternating comparator topology.These contributions show great potential for enabling closed-loop mmWave transmitters for massive MIMO transmitter realizations

Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance

Surpassing Fundamental Limits through Time Varying Electromagnetics

Surpassing the fundamental limits that govern all electromagnetic structures, such as reciprocity and the delay-bandwidth-size limit, will have a transformative impact on all applications based on electromagnetic circuits and systems. For instance, violating principles of reciprocity enables non-reciprocal components such as isolators and circulators, which find application in full-duplex wireless radios, radar, biomedical imaging, and quantum computing systems. Overcoming the delay-bandwidth-size limit enables ultra-broadband yet extremely-compact devices whose size is not fundamentally related to the wavelength at the operating frequency. The focus of this dissertation is on using time-variance as a new toolbox to overcome these fundamental limits and re-imagine circuit and system design. Traditional non-reciprocal components are realized using ferrite materials that loose their reciprocity under the application of external magnetic bias. However, the sheer volume, cost and weight of these magnet based non-reciprocal components coupled with their inability to be fabricated in conventional semiconductor processes, have limited their application to bulky and large-scale systems. Other approaches such as active-biased and non-linearity based non-reciprocity are compatible with semiconductor processes, however, they suffer from other poor linearity and noise performance. In this dissertation, using passive transistor switch as the modulating element, we have proposed the concept of spatio-temporal conductivity modulation and have demonstrated a gamut of non-reciprocal devices ranging from gyrators to isolators and circulators. Through novel circuit topologies, for the first time, we have demonstrated on-chip circulators with multi-watt input power handling, operation at high millimeter-wave frequencies, and tailor made circulators for emerging technologies such as simultaneous-transmit-and-receive MRI and quantum computing. Delay-bandwidth-size trade-off is another fundamental electromagnetic limit, that constrains the delay imparted by a medium or a device within a fixed footprint to be inversely proportional to the signal bandwidth. It is this limit that governs the size of any microwave passive devices to be inversely proportional to its operating frequency. As a part of this dissertation, through intelligent clocking of switched capacitor networks we overcame the delay-bandwidth-size limit, thus resulting in infinitesimal, yet broadband microwave devices. Here we proposed a new paradigm in wave propagation where the properties such as the propagation delay and characteristic impedance does not depend on the constituent elements/materials of the medium, but rather heavily rely on the user-defined modulation scheme, thereby opening huge opportunities for realizing highly-reconfigurable passives. Leveraging these concepts, we demonstrated wide range of reciprocal an non-reciprocal devices including ultra-compact delay elements, highly-reconfigurable microwave passives, ultra-wideband circulators with infinitesimal form-factors and dispersion-free chip scale floquet topological insulators. Application of these devices have also been evaluated in real-world systems through our demonstrations of wideband, full-duplex receivers leveraging switched capacitors based true-time-delay interference cancelers and floquet topological insulator based antenna interfaces for full-duplex phased-arrays and ultra-wideband beamformers. Furthermore, to cater the growing RF and microwave needs of future, large-scale quantum computing systems, we demonstrated a low-cryogenic, wideband circulator based on time modulation of superconducting devices. This superconducting circulator is expected to operate alongside the superconducting qubits, inside a dilution refrigerator at 10mK-100mK, thus enabling a tightly integrated quantum system. We also presented the design and implementation of a cryogenic-CMOS clock driver chip that will generate the clocks required by the superconducting circulator. Finally, we also demonstrated the design and implementation of a low-noise, low power consumption, 6GHz - 8GHz cryogenic downconversion receiver at 4K for cryogenic qubit readout

LOW-POWER FREQUENCY SYNTHESIS BASED ON INJECTION LOCKING

Ph.DDOCTOR OF PHILOSOPH

Synthèses de fréquence à bas bruit basées sur des oscillateurs opto-électroniques couplés intégrées en technologie BiCMOS SiGe 130nm

Les hyperfréquences jouent un rôle indispensable dans le domaine des télécommunications, que ce soit pour la téléphonie mobile, les radars automobiles, le Wi-Fi ou encore la transmission satellitaire, sans que cette liste ne soit évidemment exhaustive. Pour l'ensemble de ces applications omniprésentes dans la société actuelle, ce sont ces signaux hyperfréquences qui servent de porteuses pour transmettre l'information sur de plus ou moins longues distances. Les méthodes de génération de signaux hyperfréquences actuelles sont basées sur des boucles à verrouillage de phase (PLL). Elles réalisent une multiplication d'une fréquence de référence basse de quelques dizaines à quelques centaines de mégahertz pour l'amener à quelques gigahertz voire dizaines de gigahertz. Il y a cependant un inconvénient majeur lié à cette méthode : synthétiser une fréquence par multiplication d'une référence basse s'accompagne d'une augmentation théorique du bruit de phase du signal généré, d'autant plus que le rapport de multiplication est élevé. À l'inverse, une synthèse par division de fréquence diminue le bruit de phase théorique. Or on voit apparaître depuis quelques années des références à des fréquences déjà élevées, basées sur des oscillateurs optoélectroniques couplés (COEO), qui peuvent dès lors servir à réaliser des synthèses basées sur de la division de fréquence, et c'est dans ce cadre que se situe le travail de cette thèse. Nous utilisons pour référence de fréquence, des COEO qui génèrent un signal de fréquence élevée à haute pureté spectrale, à 10 et 30 GHz. L'objectif est alors d'être capable de générer des signaux dont la fréquence est inférieure à 30 GHz et aussi basse que 1 GHz. Ces signaux synthétisés doivent conserver autant que possible la pureté spectrale du signal de référence en pénalisant le moins possible le bénéfice théorique apporté par la division. Cette thèse décrit la conception de diviseurs hyperfréquences à très faible bruit de phase résiduel disposant au final de rapports de division fractionnaires et/ou programmables. Dans un premier temps, nous avons conçu des diviseurs de rapports fixes afin d'estimer les performances en bruit de phase atteignables à cette fréquence de travail sur les technologies utilisées. Plusieurs diviseurs ECL par 2 et par 3 ont été conçus, fabriqués et mesurés pour une division jusqu'à 30 GHz. Un diviseur CMOS par 10 ainsi qu'une technique de resynchronisation permettant d'annuler la majeure partie du bruit de phase de la chaîne de division sont également présentés. Plusieurs diviseurs analogiques à rang fixe ont également été conçus, bien que s'étant révélés moins performants au final : un diviseur à verrouillage par injection (ILFD) et un diviseur à renforcement du second harmonique, qui réalisent tous les deux une division par 3 autour de 30 GHz. Pour terminer, nous avons conçu des diviseurs fractionnaires large bande fonctionnant au moins jusqu'à 30 GHz et offrant des performances en bruit de phase compétitives. Si ces modèles s'inspirent du principe régénératif connu de Miller, nous en proposons une déclinaison tout à fait originale. Une première série de diviseurs fractionnaires fixes a ainsi été réalisée pour des rapports fixes de 1,25, 2,5 et 4,5. Pour terminer, un diviseur fractionnaire dont la partie décimale est programmable a été ensuite été réalisé et mesuré. Il s'agit d'un diviseur fractionnaire dont la partie entière du rapport de division est 4 et la partie décimale codée sur 4 bits.Microwave signals are essential in the field of telecommunications whether for mobile telephony, automotive radar, Wi-Fi or even satellite transmission, without this list being exhaustive. For all these ubiquitous applications in our current society, microwave signals are the carriers for the transmission of information from a system to another. Microwave signals synthesis techniques are mostly based on Phase-Locked Loop (PLL). PLL multiply a low frequency reference ranging from a dozen to a few hundred megahertz toward a few gigahertz to a few dozen gigahertz. However, there is one main drawback with this synthesis technique: synthesizing a frequency by multiplying a low frequency reference induces an unavoidable rise of the theoretical phase noise of the synthesized signal, even more if the multiplication factor is high. On the contrary, frequency synthesis by division lowers the theoretical phase noise. Yet, high frequency high spectral purity frequency references called Coupled OptoElectronic Oscillator (COEO) are being developed for a few years. They are perfect candidate to be used as reference for frequency synthesis by division, and this is within this framework that our research takes place. We use as frequency references two COEO generating high spectral purity signals at 10 and 30?GHz. The aim of our work is then to be able to generate different signals whose frequencies are below 30?GHz and as low as 1?GHz. These synthesized signals must preserve as much as possible the spectral purity of the reference while deteriorating as less as possible the theoretical benefit brought by the division. This thesis describes the conception of low residual phase noise microwave frequency dividers operating, for the most evolved ones, fractional and/or programmable division ratios. In a first place, we designed static frequency dividers in order to estimate the phase noise performance that we can conceivably reach with the technology we use. Several ECL dividers by 2 and by 3 are designed, fabricated and measured for a division up to 30?GHz. A CMOS divider by 10 along with a resynchronization technique allowing to cancel most of the phase noise in a cascaded divider are also presented. In a second place, we designed analog dividers, although they have proven to be less competitive than digital dividers: an Injection-Locked Frequency Divider (ILFD) and a regenerative second-harmonic frequency divider, both realising a frequency division by 3 around 30 GHz. Finally, we designed wideband fractional dividers operating at least at 30 GHz with competitive phase noise performance. Even though they are inspired by Miller's regenerative frequency dividers, we introduce here an innovative declination of fractional dividers. A first series of static fractional dividers has been designed with ratios of 1.25, 2.5 and 4.5. Ultimately, a fractional divider with a programmable decimal part has been designed and measured. This divider has an integer part of 4 and a decimal part programmed on 4 bits