A Software-Defined Radio Receiver Architecture Robust to Out-of-Band Interference

In a software-defined radio (SDR) receiver it is desirable to minimize RF band-filtering for flexibility, size and cost reasons, but this leads to increased out-of-band interference (OBI). Besides harmonic and intermodulation distortion (HD/IMD), OBI can also lead to blocking and harmonic mixing. A wideband LNA [1, 2] amplifies signal and interference with equal gain. Even a low gain of 6dB can clip 0dBm OBI to a 1.2V supply, blocking the receiver. Hard-switching mixers not only translate the wanted signal to baseband but also the interference around LO harmonics. Harmonic rejection (HR) mixers have been used [3, 1, 4], but are sensitive to phase and gain mismatch. Indeed the HR in [4] shows a large spread, whereas other work only shows results from one chip [3, 1]. This paper describes techniques to relax blocking and HD/IMD, and make HR robust to mismatch

A Software-Defined Radio Receiver in 65nm CMOS Robust to Out-of-Band Interference

Two techniques are presented in this paper for a software-defined radio (SDR) receiver robust to out-of-band interference. Voltage gain is realized at IF simultaneously with low-pass filtering to mitigate blockers and out-of-band intermodulation distortion. A 2-stage polyphase harmonic rejection (HR) mixer concept robust to gain error achieves 2nd-6th HR of more than 60dB for 40 samples without trimming or calibration. A prototype 0.4-0.9G zero-IF receiver in 65nm CMOS has 34dB gain, 4dB NF, +3.5dBm IIP3 and +47dBm IIP2 while drawing 50mA from 1.2V

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

Tunable, Concurrent Multiband, Single Chain Radio Architecture for Low Energy 5G-RANs

This invited paper considers a key next step in the design of radio architectures aimed at supporting low energy consumption in 5G heterogeneous radio access networks. State-of-the-art mobile radios usually require one RF transceiver per standard, each working separately at any given time. Software defined radios, while spanning a wide range of standards and frequency bands, also work separately at any specific time. In 5G radio access networks, where continuous, multiband connectivity is envisaged, this conventional radio architecture results in high network power consumption. In this paper, we propose the novel concept of a concurrent multiband frequency-agile radio (CM-FARAD) architecture, which simultaneously supports multiple standards and frequency bands using a single, tunable transceiver. We discuss the subsystem radio design approaches for enabling the CM-FARAD architecture, including antennas, power amplifiers, low noise amplifiers and analogue to digital converters. A working prototype of a dual-band CM-FARAD test-bed is also presented together with measured salient performance characteristics

RF Front End for an Integrated Silhouette Capture and Boundary Detection Frequency Modulated Continuous Wave Ultra-Wideband Radar System for the Extension of Independent Living

Limitations of current eldercare monitoring systems leave a need for new solutions. A monitoring system based on a frequency modulated continuous wave ultra-wideband short-range radar is proposed for this application. The complete proposed monitoring system is comprised of four blocks: boundary detection, silhouette capture, human identification, and data transmission. This paper develops the RF front end hardware for the silhouette capture subsystem. System requirements are derived for the silhouette capture subsystem. An architecture for the RF front end is designed, and required individual component specifications are determined. Components are selected off the shelf or custom designed for each socket. Full transmitter and receiver level plans are calculated to ensure expected system performance meets system requirements. A component library and full system schematic is created, PCB layout is completed, and PCB files are generated and sent for fabrication. PCB traces and individual components are characterized over frequency, and methods that improve inadequate performance are documented and discussed

Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios

Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the most important specifications that often face tightly coupled tradeoffs between them. To increase the data throughput, a large number of fragmented spectrums are being introduced to the wireless communication standards. Carrier aggregation technology needs concurrent communication across several non-contiguous frequency bands, which results in a rapidly growing number of band combinations. Supporting all the frequency bands and their aggregation combinations increases the complexity of the RF receivers. Highly flexible software defined radio (SDR) is a promising technology to address these applications scenarios with lower complexity by relaxing the specifications of the RF filters or eliminating them. However, there are still many technology challenges with both the receiver architecture and the circuit implementations. The performance requirements of the receivers can also vary across different application scenario and RF environments. Field-programmable dynamic performance tradeoff can potentially reduce the power consumption of the receiver. In this dissertation, we address the performance enhancement challenges in the wideband SDRs by innovations at both the circuit building block level and the receiver architecture level. A series of research projects are conducted to push the state-of-the-art performance envelope and add features such as field-programmable performance tradeoff and concurrent reception. The projects originate from the concept of thermal noise canceling techniques and further enhance the RF performance and add features for more capable SDR receivers. Four generations of prototype LNA or receiver chips are designed, and each of them pushes at least one aspect of the RF performance such as bandwidth, linearity, and NF. A noise-canceling distributed LNA breaks the tradeoff between NF and RF bandwidth by introducing microwave circuit techniques from the distributed amplifiers. The LNA architecture uniquely provides ultra high bandwidth and low NF at low frequencies. A family of field-programmable LNA realized field-programmable performance tradeoff with current-reuse programmable transconductance cells. Interferer-reflecting loops can be applied around the LNAs to improve their input linearity by rejecting the out-of-band interferers with a wideband low in- put impedance. A low noise transconductance amplifier (LNTA) that operates in class-AB-C is invented to can handle rail-to-rail out-of-band blocker without saturation. Class-AB and class-C transconductors form a composite amplifier to increase the linear range of the input voltage. A new antenna interface named frequency-translational quadrature-hybrid (FTQH) breaks the input impedance matching requirement of the LNAs by introducing quadrature hybrid couplers to the CMOS RFIC design. The FTQH receiver achieves wideband sub-1dB NF and supports scalable massive frequency-agile concurrent reception