41 research outputs found
ASSURE: RTL Locking Against an Untrusted Foundry
Semiconductor design companies are integrating proprietary intellectual
property (IP) blocks to build custom integrated circuits (IC) and fabricate
them in a third-party foundry. Unauthorized IC copies cost these companies
billions of dollars annually. While several methods have been proposed for
hardware IP obfuscation, they operate on the gate-level netlist, i.e., after
the synthesis tools embed the semantic information into the netlist. We propose
ASSURE to protect hardware IP modules operating on the register-transfer level
(RTL) description. The RTL approach has three advantages: (i) it allows
designers to obfuscate IP cores generated with many different methods (e.g.,
hardware generators, high-level synthesis tools, and pre-existing IPs). (ii) it
obfuscates the semantics of an IC before logic synthesis; (iii) it does not
require modifications to EDA flows. We perform a cost and security assessment
of ASSURE.Comment: Submitted to IEEE Transactions on VLSI Systems on 11-Oct-2020,
28-Jan-202
Optimizing the Use of Behavioral Locking for High-Level Synthesis
The globalization of the electronics supply chain requires effective methods to thwart reverse engineering and IP theft. Logic locking is a promising solution, but there are many open concerns. First, even when applied at a higher level of abstraction, locking may result in significant overhead without improving the security metric. Second, optimizing a security metric is application-dependent and designers must evaluate and compare alternative solutions. We propose a meta-framework to optimize the use of behavioral locking during the high-level synthesis (HLS) of IP cores. Our method operates on chipâs specification (before HLS) and it is compatible with all HLS tools, complementing industrial EDA flows. Our meta-framework supports different strategies to explore the design space and to select points to be locked automatically. We evaluated our method on the optimization of differential entropy, achieving better results than random or topological locking: 1) we always identify a valid solution that optimizes the security metric, while topological and random locking can generate unfeasible solutions; 2) we minimize the number of bits used for locking up to more than 90% (requiring smaller tamper-proof memories); 3) we make better use of hardware resources since we obtain similar overheads but with higher security metric
Security through Obscurity: Layout Obfuscation of Digital Integrated Circuits using Don't Care Conditions
Contemporary integrated circuits are designed and manufactured in a globalized environment leading to concerns of piracy, overproduction and counterfeiting. One class of techniques to combat these threats is circuit obfuscation which seeks to modify the gate-level (or structural) description of a circuit without affecting its functionality in order to increase the complexity and cost of reverse engineering. Most of the existing circuit obfuscation methods are based on the insertion of additional logic (called âkey gatesâ) or camouflaging existing gates in order to make it difficult for a malicious user to get the complete layout information without extensive computations to determine key-gate values. However, when the netlist or the circuit layout, although camouflaged, is available to the attacker, he/she can use advanced logic analysis and circuit simulation tools and Boolean SAT solvers to reveal the unknown gate-level information without exhaustively trying all the input vectors, thus bringing down the complexity of reverse engineering. To counter this problem, some âprovably secureâ logic encryption algorithms that emphasize methodical selection of camouflaged gates have been proposed previously in literature [1,2,3]. The contribution of this paper is the creation and simulation of a new layout obfuscation method that uses don't care conditions. We also present proof-of-concept of a new functional or logic obfuscation technique that not only conceals, but modifies the circuit functionality in addition to the gate-level description, and can be implemented automatically during the design process. Our layout obfuscation technique utilizes donât care conditions (namely, Observability and Satisfiability Donât Cares) inherent in the circuit to camouflage selected gates and modify sub-circuit functionality while meeting the overall circuit specification. Here, camouflaging or obfuscating a gate means replacing the candidate gate by a 4X1 Multiplexer which can be configured to perform all possible 2-input/ 1-output functions as proposed by Bao et al. [4]. It is important to emphasize that our approach not only obfuscates but alters sub-circuit level functionality in an attempt to make IP piracy difficult. The choice of gates to obfuscate determines the effort required to reverse engineer or brute force the design. As such, we propose a method of camouflaged gate selection based on the intersection of output logic cones. By choosing these candidate gates methodically, the complexity of reverse engineering can be made exponential, thus making it computationally very expensive to determine the true circuit functionality. We propose several heuristic algorithms to maximize the RE complexity based on donât care based obfuscation and methodical gate selection. Thus, the goal of protecting the design IP from malicious end-users is achieved. It also makes it significantly harder for rogue elements in the supply chain to use, copy or replicate the same design with a different logic. We analyze the reverse engineering complexity by applying our obfuscation algorithm on ISCAS-85 benchmarks. Our experimental results indicate that significant reverse engineering complexity can be achieved at minimal design overhead (average area overhead for the proposed layout obfuscation methods is 5.51% and average delay overhead is about 7.732%). We discuss the strengths and limitations of our approach and suggest directions that may lead to improved logic encryption algorithms in the future.
References:
[1] R. Chakraborty and S. Bhunia, âHARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection,â IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493â1502, 2009.
[2] J. A. Roy, F. Koushanfar, and I. L. Markov, âEPIC: Ending Piracy of Integrated Circuits,â in 2008 Design, Automation and Test in Europe, 2008, pp. 1069â1074.
[3] J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, âSecurity Analysis of Integrated Circuit Camouflaging,â ACM Conference on Computer Communications and Security, 2013.
[4] Bao Liu, Wang, B., "Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks,"Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , vol., no., pp.1,6, 24-28 March 2014
Design, Fabrication, and Run-time Strategies for Hardware-Assisted Security
Today, electronic computing devices are critically involved in our daily lives, basic infrastructure, and national defense systems. With the growing number of threats against them, hardware-based security features offer the best chance for building secure and trustworthy cyber systems. In this dissertation, we investigate ways of making hardware-based security into a reality with primary focus on two areas: Hardware Trojan Detection and Physically Unclonable Functions (PUFs). Hardware Trojans are malicious modifications made to original IC designs or layouts that can jeopardize the integrity of hardware and software platforms. Since most modern systems critically depend on ICs, detection of hardware Trojans has garnered significant interest in academia, industry, as well as governmental agencies. The majority of existing detection schemes focus on test-time because of the limited hardware resources available at run-time. In this dissertation, we explore innovative run-time solutions that utilize on-chip thermal sensor measurements and fundamental estimation/detection theory to expose changes in IC power/thermal profile caused by Trojan activation. The proposed solutions are low overhead and also generalizable to many other sensing modalities and problem instances. Simulation results using state-of-the-art tools on publicly available Trojan benchmarks verify that our approaches can detect Trojans quickly and with few false positives. Physically Unclonable Functions (PUFs) are circuits that rely on IC fabrication variations to generate unique signatures for various security applications such as IC authentication, anti-counterfeiting, cryptographic key generation, and tamper resistance. While the existence of variations has been well exploited in PUF design, knowledge of exactly how variations come into existence has largely been ignored. Yet, for several decades the Design-for-Manufacturability (DFM) community has actually investigated the fundamental sources of these variations. Furthermore, since manufacturing variations are often harmful to IC yield, the existing DFM tools have been geared towards suppressing them (counter-intuitive for PUFs). In this dissertation, we make several improvements over current state-of-the-art work in PUFs. First, our approaches exploit existing DFM models to improve PUFs at physical layout and mask generation levels. Second, our proposed algorithms reverse the role of standard DFM tools and extend them towards improving PUF quality without harming non-PUF portions of the IC. Finally, since our approaches occur after design and before fabrication, they are applicable to all types of PUFs and have little overhead in terms of area, power, etc. The innovative and unconventional techniques presented in this dissertation should act as important building blocks for future work in cyber security
Law and the political economy of AI production
The governance of artificial intelligence (AI) is at a historical juncture. Legislative acts, global treaties, export controls, and technical standards are now dominating the discourse over what used to be a predominantly market-driven space. Amidst all this frenzy, this paper explains why none of these projects will achieve âalignmentâ of AI with the prospect of a sustainable model of production authentically committed to the rights and freedoms of people and communities. By reflecting on the role of law in consolidating the visions and logics of few multinationals in the global value chains of AI, it warns against the peril of regulating AI without looking at the methods and logistics of its material production. Following a detailed overview of the various (techno-)legal ways through which law enables the flow of materials, capital, and power from Global South to Global North, and from small players to lead firms, the paper concludes with some preliminary thoughts on a transformative agenda for the transnational regulation of infocomputational production
Trusted SoC Realization for Remote Dynamic IP Integration
Heutzutage bieten field-programmable gate arrays (FPGAs) enorme Rechenleistung und FlexibilitĂ€t. Zudem sind sie oft auf einem einzigen Chip mit eingebetteten Multicore-Prozessoren, DSP-Engines und Speicher-Controllern integriert. Dadurch sind sie fĂŒr groĂe und komplexe Anwendungen geeignet. Gleichzeitig fĂŒhrten die Fortschritte auf dem Gebiet der High-Level-Synthese und die VerfĂŒgbarkeit standardisierter Schnittstellen (wie etwa das Advanced eXtensible Interface 4) zur Entwicklung spezialisierter und neuartiger FunktionalitĂ€ten durch DesignhĂ€user. All dies schuf einen Bedarf fĂŒr ein Outsourcing der Entwicklung oder die Lizenzierung von FPGA-IPs (Intellectual Property). Ein Pay-per-Use IP-Lizenzierungsmodell, bei dem diese IPs vor allen Marktteilnehmern geschĂŒtzt sind, kommt den Entwicklern der IPs zugute. AuĂerdem handelt es sich bei den Entwicklern von FPGA-Systemen in der Regel um kleine bis mittlere Unternehmen, die in Bezug auf die MarkteinfĂŒhrungszeit und die Kosten pro Einheit von einem solchen Lizenzierungsmodell profitieren können.
Im akademischen Bereich und in der Industrie gibt es mehrere IP-Lizenzierungsmodelle und Schutzlösungen, die eingesetzt werden können, die jedoch mit zahlreichen Sicherheitsproblemen behaftet sind. In einigen FĂ€llen verursachen die vorgeschlagenen SicherheitsmaĂnahmen einen unnötigen Ressourcenaufwand und EinschrĂ€nkungen fĂŒr die Systementwickler, d. h., sie können wesentliche Funktionen ihres GerĂ€ts nicht nutzen. DarĂŒber hinaus lassen sie zwei funktionale Herausforderungen auĂer Acht: das Floorplanning der IP auf der programmierbaren Logik (PL) und die Generierung des Endprodukts der IP (Bitstream) unabhĂ€ngig vom Gesamtdesign.
In dieser Arbeit wird ein Pay-per-Use-Lizenzierungsschema vorgeschlagen und unter Verwendung eines security framework (SFW) realisiert, um all diese Herausforderungen anzugehen. Das vorgestellte Schema ist pragmatisch, weniger restriktiv fĂŒr Systementwickler und bietet Sicherheit gegen IP-Diebstahl. DarĂŒber hinaus werden MaĂnahmen ergriffen, um das System vor einem IP zu schĂŒtzen, das bösartige Schaltkreise enthĂ€lt. Das âSecure Frameworkâ umfasst ein vertrauenswĂŒrdiges Betriebssystem, ein reichhaltiges Betriebssystem, mehrere unterstĂŒtzende Komponenten (z. B. TrustZone- Logik, gegen Seitenkanalangriffe (SCA) resistente EntschlĂŒsselungsschaltungen) und Softwarekomponenten, z. B. fĂŒr die Bitstromanalyse. Ein GerĂ€t, auf dem das SFW lĂ€uft, kann als vertrauenswĂŒrdiges GerĂ€t betrachtet werden, das direkt mit einem Repository oder einem IP-Core-Entwickler kommunizieren kann, um IPs in verschlĂŒsselter Form zu erwerben. Die EntschlĂŒsselung und Authentifizierung des IPs erfolgt auf dem GerĂ€t, was die AngriffsflĂ€che verringert und es weniger anfĂ€llig fĂŒr IP-Diebstahl macht. AuĂerdem werden Klartext-IPs in einem geschĂŒtzten Speicher des vertrauenswĂŒrdigen Betriebssystems abgelegt. Das Klartext-IP wird dann analysiert und nur dann auf der programmierbaren Logik konfiguriert, wenn es authentisch ist und keine bösartigen Schaltungen enthĂ€lt. Die Bitstrom-AnalysefunktionalitĂ€t und die SFW-Unterkomponenten ermöglichen die Partitionierung der PL-Ressourcen in sichere und unsichere Ressourcen, d. h. die Erweiterung desKonzepts der vertrauenswĂŒrdigen AusfĂŒhrungsumgebung (TEE) auf die PL. Dies ist die erste Arbeit, die das TEE-Konzept auf die programmierbare Logik ausweitet.
Bei der oben erwĂ€hnten SCA-resistenten EntschlĂŒsselungsschaltung handelt es sich um die Implementierung des Advanced Encryption Standard, der so modifiziert wurde, dass er gegen elektromagnetische und stromverbrauchsbedingte Leckagen resistent ist. Das geschĂŒtzte Design verfĂŒgt ĂŒber zwei GegenmaĂnahmen, wobei die erste auf einer Vielzahl unterschiedler Implementierungsvarianten und verĂ€nderlichen Zielpositionen bei der Konfiguration basiert, wĂ€hrend die zweite nur unterschiedliche Implementierungsvarianten verwendet. Diese GegenmaĂnahmen sind auch wĂ€hrend der Laufzeit skalierbar. Bei der Bewertung werden auch die Auswirkungen der Skalierbarkeit auf den FlĂ€chenbedarf und die SicherheitsstĂ€rke berĂŒcksichtigt.
DarĂŒber hinaus wird die zuvor erwĂ€hnte funktionale Herausforderung des IP Floorplanning durch den Vorschlag eines feinkörnigen Automatic Floorplanners angegangen, der auf gemischt-ganzzahliger linearer Programmierung basiert und aktuelle FPGAGenerationen mit gröĂeren und komplexen Bausteine unterstĂŒtzt. Der Floorplanner bildet eine Reihe von IPs auf dem FPGA ab, indem er prĂ€zise rekonfigurierbare Regionen schafft. Dadurch werden die verbleibenden verfĂŒgbaren Ressourcen fĂŒr das Gesamtdesign maximiert. Die zweite funktionale Herausforderung besteht darin, dass die vorhandenen Tools keine native FunktionalitĂ€t zur Erzeugung von IPs in einer eigenstĂ€ndigen Umgebung bieten. Diese Herausforderung wird durch den Vorschlag eines unabhĂ€ngigen IP-Generierungsansatzes angegangen. Dieser Ansatz kann von den Marktteilnehmern verwendet werden, um IPs eines Entwurfs unabhĂ€ngig vom Gesamtentwurf zu generieren, ohne die KompatibilitĂ€t der IPs mit dem Gesamtentwurf zu beeintrĂ€chtigen
Survey on Additive Manufacturing, Cloud 3D Printing and Services
Cloud Manufacturing (CM) is the concept of using manufacturing resources in a
service oriented way over the Internet. Recent developments in Additive
Manufacturing (AM) are making it possible to utilise resources ad-hoc as
replacement for traditional manufacturing resources in case of spontaneous
problems in the established manufacturing processes. In order to be of use in
these scenarios the AM resources must adhere to a strict principle of
transparency and service composition in adherence to the Cloud Computing (CC)
paradigm. With this review we provide an overview over CM, AM and relevant
domains as well as present the historical development of scientific research in
these fields, starting from 2002. Part of this work is also a meta-review on
the domain to further detail its development and structure