Semiconductor design companies are integrating proprietary intellectual
property (IP) blocks to build custom integrated circuits (IC) and fabricate
them in a third-party foundry. Unauthorized IC copies cost these companies
billions of dollars annually. While several methods have been proposed for
hardware IP obfuscation, they operate on the gate-level netlist, i.e., after
the synthesis tools embed the semantic information into the netlist. We propose
ASSURE to protect hardware IP modules operating on the register-transfer level
(RTL) description. The RTL approach has three advantages: (i) it allows
designers to obfuscate IP cores generated with many different methods (e.g.,
hardware generators, high-level synthesis tools, and pre-existing IPs). (ii) it
obfuscates the semantics of an IC before logic synthesis; (iii) it does not
require modifications to EDA flows. We perform a cost and security assessment
of ASSURE.Comment: Submitted to IEEE Transactions on VLSI Systems on 11-Oct-2020,
28-Jan-202
