A VLSI Array Architecture for Realization of DFT, DHT, DCT and DST

A unified array architecture is described for computation of DFT, DHT, DCT and DST using a modified CORDIC (CoOrdinate Rotation DIgital Computer) arithmetic unit as the basic Processing Element (PE). All these four transforms can be computed by simple rearrangement of input samples. Compared to five other existing architectures, this one has the advantage in speed in terms of latency and throughput. Moreover, the simple local neighborhood interprocessor connections make it convenient for VLSI implementation. The architecture can be extended to compute transformation of longer length by judicially cascading the modules of shorter transformation length which will be suitable for Wafer Scale Integration (WSI). CORDIC is designed using Transmission Gate Logic (TGL) on sea of gates semicustom environment. Simulation results show that this architecture may be a suitable candidate for low power/low voltage applications

Two- and Three-dimensional High Performance, Patterned Overlay Multi-chip Module Technology

A two- and three-dimensional multi-chip module technology was developed in response to the continuum in demand for increased performance in electronic systems, as well as the desire to reduce the size, weight, and power of space systems. Though developed to satisfy the needs of military programs, such as the Strategic Defense Initiative Organization, the technology, referred to as High Density Interconnect, can also be advantageously exploited for a wide variety of commercial applications, ranging from computer workstations to instrumentation and microwave telecommunications. The robustness of the technology, as well as its high performance, make this generality in application possible. More encouraging is the possibility of this technology for achieving low cost through high volume usage

A Raspberry Pi controlling neuromorphic hardware

This thesis describes the integration of a Raspberry Pi, a credit-card-sized single board computer, into the Wafer Scale Integration (WSI) System of the BrainScaleS project. The Raspberry Pi’s task is to bundle all the interfaces necessary to manage the system’s elaborate power supply into one single-access, easy-to-use interface. To this purpose the Raspberry Pi replaced the former evaluation board responsible for power management, taking over all of its tasks and in addition providing faster and cheaper hardware. The integration took place in two main steps: configuring the Raspberry Pi’s hardware and adapting the control programme from the former board to the new hardware. The results of this thesis are the successful integration of the Raspberry Pi into the WSI system, which was proven by several communication tests between the Raspberry Pi and the rest of the system, and an easy-to-follow step-by-step guide on how to set up Raspberry Pis to manage additional systems

Efficient algorithms for reconfiguration in VLSI/WSI arrays

The issue of developing efficient algorithms for reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources is discussed. The models discussed consist of a set of identical processors embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. An array grid model based on single-track switches is considered. An efficient polynomial time algorithm is proposed for determining feasible reconfigurations for an array with a given distribution of faulty processors. In the process, it is shown that the set of conditions in the reconfigurability theorem is not necessary. A polynomial time algorithm is developed for finding feasible reconfigurations in an augmented single-track model and in array grid models with multiple-track switche

A self-reconfigurable hardware architecture for mesh arrays using single/double vertical track switches

科研費報告書収録論文(課題番号:14380138・基盤研究(B)(2)・14～16/研究代表者:堀口, 進 死亡(奥様 堀口悦子)/超高速ノンブロック・ネットワーク構成方式に関する研究

DESIGN METHODOLOGIES AND SOME ASPECTS OF VLSI AND ULSI

This is a review and considers first technical aspects and drawbacks for realizing very large scale and wafer scale integrated circuits. Among these are small geometry effects and interconnection delay. Some solutions are considered. Next, design methodologies for VLSI are discussed, considering the hierarchy of VLSI systems. Finally the influences for students education are remarked and a design system consisting of CAD tools for logic synthesis and simulation, network-and device simulation, automated layout generation and layout-verification are described

PIC based hand-held IC tester

Nowadays, electrical devices are very common in our life, for example televisions, computers, cellular phones, remote control, automobile etc. All the electrical devices consist of integrated circuits (ICs). As the FKEE students, dealing with ICs has become a norm. However, the IC tester used in laboratory to verify the availability of the ICs is big, not portable, heavy and expensive. Thus, a hand-held IC tester is developed to test common ICs used in the laboratory. In this project, the microcontroller used is PIC18F4525 to control the operation of the system. In addition, it is equipped with a numerical keypad, keypad encoder, IC socket, liquid crystal display screen, beeper and a 9V cell battery power supply. The ICs to-be-tested will be placed into IC socket. The code of the IC will be keyed in by using the keypad. Then, the outcome of the test will be shown at the LCD screen and beeper to indicate the status of the ICs. The system is compact, portable and can test various forms of 20 pins ICs such as basic logic gate, multiplexer, de-multiplexer, encoder, decoder, counter, flip-flop, and etc

Efficient reconfigurable techniques for VLSI arrays with 6-port switches

This paper proposes an efficient techniques to reconfigure a two-dimensional degradable very large scale integration/wafer scale integration (VLSI/WSI) array under the row and column routing constraints, which has been shown to be NP-complete. The proposed VLSI/WSI array consists of identical processing elements such as processors or memory cells embedded in a 6-port switch lattice in the form of a rectangular grid. It has been shown that the proposed VLSI structure with 6-port switches eliminates the need to incorporate internal bypass within processing elements and leads to notable increase in the harvest when compared with the one using 4-port switches. A new greedy rerouting algorithm and compensation approaches are also proposed to maximize harvest through reconfiguration. Experimental results show that the proposed VLSI array with 6-port switches consistently outperforms the most efficient alternative, proposed in literature, toward maximizing the harvest in the presence of fault processing elements

Architectures for block Toeplitz systems

In this paper efficient VLSI architectures of highly concurrent algorithms for the solution of block linear systems with Toeplitz or near-to-Toeplitz entries are presented. The main features of the proposed scheme are the use of scalar only operations, multiplications/divisions and additions, and the local communication which enables the development of wavefront array architecture. Both the mean squared error and the total squared error formulations are described and a variety of implementations are given

Three Dimensional Integration (3DI) of semiconductor circuit layers: new devices and fabrication process

The device density of Integrated Circuits (ICs) manufactured by current VLSI technology is reaching it\u27s theoretical limit. Nevertheless, the demand for integration of more devices per chip is growing. To accommodate this need three main possibilities can be explored: Wafer Scale Integration (WSI), Ultra Large Scale Integration (ULSI), and Three Dimensional Integration (3DI). A brief review of these techniques along with their comparative advantages and disadvantages is presented. It has been concluded that 3DI technology is superior to others. Therefore, an attempt is made to develop a viable fabrication process for this technology. This is done by first reviewing the current technologies that are utilized for fabrication of Integrated Circuits (ICs) and their compatibility with 3DI stringent requirements.;Based on this review, a set of fabrication procedure for realization of 3DI technology, are presented in chapter 3. In Chapter 1 the compatibility of the currently used devices, such as BJTs and FETS, with 3DI technology is examined. Moreover, a new active device is developed for 3DI technology to replace BJTs and FETs in circuits. This new device is more compatible to the constrains of 3DI technology. Chapter 2 is devoted to solving the overall problems of 3DI circuits. The problem of heat and power dispassion and signal coupling (Cross-Talk) between the layers are reviewed, and an inter-layer shield is proposed to overcome these problems. The effectiveness of such a thin shield is considered theoretically. In Chapter 3 a fabrication process for 3DI technology is proposed. This is done after a short analysis of previous attempts in developing 3DI technologies.;Chapter 4 focuses on analog extension of 3DI technology. Moreover, in this chapter microwave 3DI circuits or 3DI MMIC is investigated. Practical considerations in choice of material for the proposed device is the subject of study in Chapter 5. Low temperature ohmic contact and utilization of metal-silicides for the proposed device are considered in this chapter. Finally in Chapter 6 various computer verifications for this work is presented, and in Chapter 7 experimental results to support this work is included