The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Integrated circuit outlier identification by multiple parameter correlation

Semiconductor manufacturers must ensure that chips conform to their specifications before they are shipped to customers. This is achieved by testing various parameters of a chip to determine whether it is defective or not. Separating defective chips from fault-free ones is relatively straightforward for functional or other Boolean tests that produce a go/no-go type of result. However, making this distinction is extremely challenging for parametric tests. Owing to continuous distributions of parameters, any pass/fail threshold results in yield loss and/or test escapes. The continuous advances in process technology, increased process variations and inaccurate fault models all make this even worse. The pass/fail thresholds for such tests are usually set using prior experience or by a combination of visual inspection and engineering judgment. Many chips have parameters that exceed certain thresholds but pass Boolean tests. Owing to the imperfect nature of tests, to determine whether these chips (called "outliers") are indeed defective is nontrivial. To avoid wasted investment in packaging or further testing it is important to screen defective chips early in a test flow. Moreover, if seemingly strange behavior of outlier chips can be explained with the help of certain process parameters or by correlating additional test data, such chips can be retained in the test flow before they are proved to be fatally flawed. In this research, we investigate several methods to identify true outliers (defective chips, or chips that lead to functional failure) from apparent outliers (seemingly defective, but fault-free chips). The outlier identification methods in this research primarily rely on wafer-level spatial correlation, but also use additional test parameters. These methods are evaluated and validated using industrial test data. The potential of these methods to reduce burn-in is discussed

Cost modelling and concurrent engineering for testable design

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.As integrated circuits and printed circuit boards increase in complexity, testing becomes a major cost factor of the design and production of the complex devices. Testability has to be considered during the design of complex electronic systems, and automatic test systems have to be used in order to facilitate the test. This fact is now widely accepted in industry. Both design for testability and the usage of automatic test systems aim at reducing the cost of production testing or, sometimes, making it possible at all. Many design for testability methods and test systems are available which can be configured into a production test strategy, in order to achieve high quality of the final product. The designer has to select from the various options for creating a test strategy, by maximising the quality and minimising the total cost for the electronic system. This thesis presents a methodology for test strategy generation which is based on consideration of the economics during the life cycle of the electronic system. This methodology is a concurrent engineering approach which takes into account all effects of a test strategy on the electronic system during its life cycle by evaluating its related cost. This objective methodology is used in an original test strategy planning advisory system, which allows for test strategy planning for VLSI circuits as well as for digital electronic systems. The cost models which are used for evaluating the economics of test strategies are described in detail and the test strategy planning system is presented. A methodology for making decisions which are based on estimated costing data is presented. Results of using the cost models and the test strategy planning system for evaluating the economics of test strategies for selected industrial designs are presented

Advanced Applications of Rapid Prototyping Technology in Modern Engineering

Rapid prototyping (RP) technology has been widely known and appreciated due to its flexible and customized manufacturing capabilities. The widely studied RP techniques include stereolithography apparatus (SLA), selective laser sintering (SLS), three-dimensional printing (3DP), fused deposition modeling (FDM), 3D plotting, solid ground curing (SGC), multiphase jet solidification (MJS), laminated object manufacturing (LOM). Different techniques are associated with different materials and/or processing principles and thus are devoted to specific applications. RP technology has no longer been only for prototype building rather has been extended for real industrial manufacturing solutions. Today, the RP technology has contributed to almost all engineering areas that include mechanical, materials, industrial, aerospace, electrical and most recently biomedical engineering. This book aims to present the advanced development of RP technologies in various engineering areas as the solutions to the real world engineering problems

Modelling and simulation of paradigms for printed circuit board assembly to support the UK's competency in high reliability electronics

The fundamental requirement of the research reported within this thesis is the provision of physical models to enable model based simulation of mainstream printed circuit assembly (PCA) process discrete events for use within to-be-developed (or under development) software tools which codify cause & effects knowledge for use in product and process design optimisation. To support a national competitive advantage in high reliability electronics UK based producers of aircraft electronic subsystems require advanced simulation tools which offer model based guidance. In turn, maximization of manufacturability and minimization of uncontrolled rework must therefore enhance inservice sustainability for ‘power-by-the-hour’ commercial aircraft operation business models. [Continues.

NASA Tech Briefs, July 2012

Topics covered include: Instrument Suite for Vertical Characterization of the Ionosphere-Thermosphere System; Terahertz Radiation Heterodyne Detector Using Two-Dimensional Electron Gas in a GaN Heterostructure; Pattern Recognition Algorithm for High-Sensitivity Odorant Detection in Unknown Environments; Determining Performance Acceptability of Electrochemical Oxygen Sensors; Versatile Controller for Infrared Lamp and Heater Arrays; High-Speed Scanning Interferometer Using CMOS Image Sensor and FPGA Based on Multifrequency Phase-Tracking Detection; Ultra-Low-Power MEMS Selective Gas Sensors; Compact Receiver Front Ends for Submillimeter-Wave Applications; Dynamically Reconfigurable Systolic Array Accelerator; Blocking Losses With a Photon Counter; Motion-Capture-Enabled Software for Gestural Control of 3D Mod; Orbit Software Suite; CoNNeCT Baseband Processor Module Boot Code SoftWare (BCSW); Trajectory Software With Upper Atmosphere Model; ALSSAT Version 6.0; Employing a Grinding Technology to Assess the Microbial Density for Encapsulated Organisms; Demonstration of Minimally Machined Honeycomb Silicon Carbide Mirrors; Polyimide Aerogel Thin Films; Nanoengineered Thermal Materials Based on Carbon Nanotube Array Composites; Composite Laminate With Coefficient of Thermal Expansion Matching D263 Glass; Robust Tensioned Kevlar Suspension Design; Focal Plane Alignment Utilizing Optical CMM; Purifying, Separating, and Concentrating Cells From a Sample Low in Biomass; Virtual Ultrasound Guidance for Inexperienced Operators; Beat-to-Beat Blood Pressure Monitor; Non-Contact Conductivity Measurement for Automated Sample Processing Systems; An MSK Radar Waveform; Telescope Alignment From Sparsely Sampled Wavefront Measurements Over Pupil Subapertures; Method to Remove Particulate Matter from Dusty Gases at Low Pressures; Terahertz Quantum Cascade Laser With Efficient Coupling and Beam Profile; Measurement Via Optical Near-Nulling and Subaperture Stitching; 885-nm Pumped Ceramic Nd:YAG Master Oscillator Power Amplifier Laser System; Airborne Hyperspectral Imaging System; Heat Shield Employing Cured Thermal Protection Material Blocks Bonded in a Large-Cell Honeycomb Matrix; and Asymmetric Supercapacitor for Long-Duration Power Storage

A COMPREHENSIVE ASSESSMENT METHODOLOGY BASED ON LIFE CYCLE ANALYSIS FOR ON-BOARD PHOTOVOLTAIC SOLAR MODULES IN VEHICLES

This dissertation presents a novel comprehensive assessment methodology for using on-board photovoltaic (PV) solar technologies in vehicle applications. A well-to-wheels life cycle analysis based on a unique energy, greenhouse gas (GHG) emission, and economic perspective is carried out in the context of meeting corporate average fuel economy (CAFE) standards through 2025 along with providing an alternative energy path for the purpose of sustainable transportation. The study includes 14 different vehicles, 3 different travel patterns, in 12 U.S. states and 16 nations using 19 different cost analysis scenarios for determining the challenges and benefits of using on-board photovoltaic (PV) solar technologies in vehicle applications. It develops a tool for decision-makers and presents a series of design requirements for the implementation of on-board PV in automobiles to use during the conceptual design stage, since its results are capable of reflecting the changes in fuel consumption, greenhouse gas emission, and cost for different locations, technological, and vehicle sizes. The decision-supports systems developed include (i) a unique decision support systems for selecting the optimal PV type for vehicle applications using quality function deployment, analytic hierarchy process, and fuzzy axiomatic design, (ii) a unique system for evaluating all non-destructive inspection systems for defects in the PV device to select the optimum system suitable for an automated PV production line. (iii) The development of a comprehensive PV system model that for predicting the impact of using on-board PV based on life cycle assessment perspective. This comprehensive assessment methodology is a novel in three respects. First, the proposed work develops a comprehensive PV system model and optimizes the solar energy to DC electrical power output ratio. Next, it predicts the actual contribution of the on-board PV to reduce fuel consumption, particularly for meeting corporate average fuel economy (CAFE) 2020 and 2025 standards in different scenarios. The model also estimates vehicle range extension via on-board PV and enhances the current understanding regarding the applicability and effective use of on-board PV modules in individual automobiles. Finally, it develops a life cycle assessment (LCA) model (well-to-wheels analysis) for this application. This enables a comprehensive assessment of the effectiveness of an on-board PV vehicle application from an energy consumption, Greenhouse Gas (GHG) emission, and cost life-cycle perspective. The results show that by adding on-board PVs to cover less than 50% of the projected horizontal surface area of a typical passenger vehicle, up to 50% of the total daily miles traveled by a person in the U.S. could be driven by solar energy if using a typical mid-size vehicle, and up to 174% if using a very lightweight and aerodynamically efficient vehicle. In addition, the increase in fuel economy in terms of combined mile per gallon (MPG) at noon for heavy vehicles is between 2.9% to 9.5%. There is a very significant increase for lightweight and aerodynamic efficient vehicles, with MPG increase in the range of 10.7% to 42.2%, depending on location and time of year. Although the results show that the plug-in electric vehicles (EVs) do not always have a positive environmental impact over similar gasoline vehicles considering the well-to-wheel span, the addition of an on-board PV system for both vehicle configurations, significantly reduces cycle emissions (e.g., the equivalent savings of what an average U.S. home produces in a 20 month period). The lifetime driving cost ($per mile) of a gasoline vehicle with adding on-board PV, compared to a pure gasoline vehicle, is lower in regions with more sunlight (e.g., Arizona) even of the current gasoline price in the U.S. ($4.0 per gallon) assuming battery costs will decline over time. Lifetime driving cost ($per mile) of a plug-in EV with added PV versus pure plug-in EV (assuming electricity price 0.18$/kWh) is at least similar, but mostly lower, even in regions with less sunlight (e.g., Massachusetts). In places with low electricity prices (0.13 $/kWh), and with more sunlight, the costs of operating an EV with PV are naturally lower. The study reports a unique observation that placing PV systems on-board for existing vehicles is in some cases superior to the lightweighting approach regarding full fuel-cycle emissions. An added benefit of on-board PV applications is the ability to incorporate additional functionality into vehicles. Results show that an on-board PV system operating in Phoenix, AZ can generate in its lifetime, energy that is the equivalent of what an American average household residential utility customer consumes over a three-year period. However, if the proposed system operates in New Delhi, India, the PV could generate energy in its lifetime that is the equivalent of what an Indian average household residential utility customer consumes over a 33-year period. Consequently, this proposed application transforms, in times of no-use, into a flexible energy generation system that can be fed into the grid and used to power electrical devices in homes and offices. The fact that the output of this system is direct current (DC) electricity rather than alternative current (AC) electricity reduces the wasted energy cost in the generation, transmission, and conversion losses between AC-DC electricity to reach the grid. Thus, this system can potentially reduce the dependency on the grid in third world countries where the energy consumption per home is limited and the grid is unstable or unreliable, or even unavailable

The 2020 photovoltaic technologies roadmap

Over the past decade, the global cumulative installed photovoltaic (PV) capacity has grown exponentially, reaching 591 GW in 2019. Rapid progress was driven in large part by improvements in solar cell and module efficiencies, reduction in manufacturing costs and the realization of levelized costs of electricity that are now generally less than other energy sources and approaching similar costs with storage included. Given this success, it is a particularly fitting time to assess the state of the photovoltaics field and the technology milestones that must be achieved to maximize future impact and forward momentum. This roadmap outlines the critical areas of development in all of the major PV conversion technologies, advances needed to enable terawatt-scale PV installation, and cross-cutting topics on reliability, characterization, and applications. Each perspective provides a status update, summarizes the limiting immediate and long-term technical challenges and highlights breakthroughs that are needed to address them. In total, this roadmap is intended to guide researchers, funding agencies and industry in identifying the areas of development that will have the most impact on PV technology in the upcoming years

Cross-Layer Pathfinding for Off-Chip Interconnects

Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects