Algorithms for Circuit Sizing in VLSI Design

One of the key problems in the physical design of computer chips, also known as integrated circuits, consists of choosing a  physical layout  for the logic gates and memory circuits (registers) on the chip. The layouts have a high influence on the power consumption and area of the chip and the delay of signal paths.  A discrete set of predefined layouts  for each logic function and register type with different physical properties is given by a library. One of the most influential characteristics of a circuit defined by the layout is its size. In this thesis we present new algorithms for the problem of choosing sizes for the circuits and its continuous relaxation,  and  evaluate these in theory and practice. A popular approach is based on Lagrangian relaxation and projected subgradient methods. We show that seemingly heuristic modifications that have been proposed for this approach can be theoretically justified by applying the well-known multiplicative weights algorithm. Subsequently, we propose a new model for the sizing problem as a min-max resource sharing problem. In our context, power consumption and signal delays are represented by resources that are distributed to customers. Under certain assumptions we obtain a polynomial time approximation for the continuous relaxation of the sizing problem that improves over the Lagrangian relaxation based approach. The new resource sharing algorithm has been implemented as part of the BonnTools software package which is developed at the Research Institute for Discrete Mathematics at the University of Bonn in cooperation with IBM. Our experiments on the ISPD 2013 benchmarks and state-of-the-art microprocessor designs provided by IBM illustrate that the new algorithm exhibits more stable convergence behavior compared to a Lagrangian relaxation based algorithm. Additionally, better timing and reduced power consumption was achieved on almost all instances. A subproblem of the new algorithm consists of finding sizes minimizing a weighted sum of power consumption and signal delays. We describe a method that approximates the continuous relaxation of this problem in polynomial time under certain assumptions. For the discrete problem we provide a fully polynomial approximation scheme under certain assumptions on the topology of the chip. Finally, we present a new algorithm for timing-driven optimization of registers. Their sizes and locations on a chip are usually determined during the clock network design phase, and remain mostly unchanged afterwards although the timing criticalities on which they were based can change. Our algorithm permutes register positions and sizes within so-called  clusters  without impairing the clock network such that it can be applied late in a design flow. Under mild assumptions, our algorithm finds an optimal solution which maximizes the worst cluster slack. It is implemented as part of the BonnTools and improves timing of registers on state-of-the-art microprocessor designs by up to 7.8% of design cycle time. </div

Optimization of Vortex Tube Design and Performance for Cooling Milling Process

The manufacturing process is required to improve cleanliness and reduce environmental pollution and the exploration of natural resources is limited. One of the manufacturing processes is machining, especially the milling process. The phenomenon during the milling process friction occurs when the workpiece is cut by the milling tool, the effect friction between tool and workpiece occurs temperature rise. To reduce the temperature rise of the milling tool during the workpiece cutting process, an effective and efficient alternative cooling is needed through the use of vortex tubes. The research method was carried out using the Computational Fluid Dynamic (CFD) approach and experiments with the use of inlet pressure = 1-5 Bar, and the parameters of variations in valve shape, number of nozzles, and pipe lengths. The overall results of the CFD and experiment of parameters in inlet pressure on the number of nozzles, valve shapes, and tube lengths, have an impact on the increasing inlet pressure, the higher the thermodynamic characteristics that occur in the vortex tube, but there is a loss of outlet pressure in each parameter. The geometry of the vortex tube selected is the number of nozzles 6, valve fillet shape, and tube length of 50 mm, vortex tube can be used for cooling the milling tool with the addition of a flexible hose at a distance of 5 cm from the tooltip

Optimization of Vortex Tube Design and Performance for Cooling Milling Process

The manufacturing process is required to improve cleanliness and reduce environmental pollution and the exploration of natural resources is limited. One of the manufacturing processes is machining, especially the milling process. The phenomenon during the milling process friction occurs when the workpiece is cut by the milling tool, the effect friction between tool and workpiece occurs temperature rise. To reduce the temperature rise of the milling tool during the workpiece cutting process, an effective and efficient alternative cooling is needed through the use of vortex tubes. The research method was carried out using the Computational Fluid Dynamic (CFD) approach and experiments with the use of inlet pressure = 1-5 Bar, and the parameters of variations in valve shape, number of nozzles, and pipe lengths. The overall results of the CFD and experiment of parameters in inlet pressure on the number of nozzles, valve shapes, and tube lengths, have an impact on the increasing inlet pressure, the higher the thermodynamic characteristics that occur in the vortex tube, but there is a loss of outlet pressure in each parameter. The geometry of the vortex tube selected is the number of nozzles 6, valve fillet shape, and tube length of 50 mm, vortex tube can be used for cooling the milling tool with the addition of a flexible hose at a distance of 5 cm from the tooltip

IMPACT OF DYNAMIC VOLTAGE SCALING (DVS) ON CIRCUIT OPTIMIZATION

Circuit designers perform optimization procedures targeting speed and power during the design of a circuit. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied to optimize for leakage and dynamic power, respectively. Both gate sizing and Dual-VT are design-time techniques, which are applied to the circuit at a fixed voltage. On the other hand, DVS is a run-time technique and implies that the circuit will be operating at a different voltage than that used during the optimization phase at design-time. After some analysis, the risk of non-critical paths becoming critical paths at run-time is detected under these circumstances. The following questions arise: 1) should we take DVS into account during the optimization phase? 2) Does DVS impose any restrictions while performing design-time circuit optimizations?. This thesis is a case study of applying DVS to a circuit that has been optimized for speed and power, and aims at answering the previous two questions. We used a 45-nm CMOS design kit and flow. Synthesis, placement and routing, and timing analysis were applied to the benchmark circuit ISCAS?85 c432. Logical Effort and Dual-VT algorithms were implemented and applied to the circuit to optimize for speed and leakage power, respectively. Optimizations were run for the circuit operating at different voltages. Finally, the impact of DVS on circuit optimization was studied based on HSPICE simulations sweeping the supply voltage for each optimization. The results showed that DVS had no impact on gate sizing optimizations, but it did on Dual-VT optimizations. It is shown that we should not optimize at an arbitrary voltage. Moreover, simulations showed that Dual-VT optimizations should be performed at the lowest voltage that DVS is intended to operate, otherwise non-critical paths will become critical paths at run-time

A new approach to sensitivity climatologies: the DTS-MEDEX-2009 campaign

Adaptive observation is an approach to improving the quality of numerical weather forecasts through the optimization of observing networks. It is sometimes referred to as Data Targeting (DT). This approach has been applied to high impact weather during specific field campaigns in the past decade. Adaptive observations may involve various types of observations, including either specific research observing platforms or routine observing platforms employed in an adaptive way. The North-Atlantic TReC 2003 and the EURORISK-PREVIEW 2008 exercises focused on the North-Atlantic and Western Europe areas using mainly routine observing systems. These campaigns also included Mediterranean cases. &lt;br&gt;&lt;br&gt; The most recent campaign, DTS-MEDEX-2009, is the first campaign in which the DT method has been used to address exclusively Mediterranean high impact weather events. In this campaign, which is an important stage in the MEDEX development, only operational radiosonde stations and commercial aircraft data (AMDAR) have provided additional observations. Although specific diagnostic studies are needed to assess the impact of the extra-observations on forecast skill and demonstrate the effectiveness of DTS-MEDEX-2009, some preliminary findings can be deduced from a survey of this targeting exercise. &lt;br&gt;&lt;br&gt; After a description of the data targeting system and some illustrations of particular cases, this paper attempts some comparisons of additional observation needs (through effectively deployed radio-soundings) with sensitivity climatologies in the Mediterranean. The first step towards a sensitivity climatology for Mediterranean cases of high impact weather is indirectly given by the frequency of extra-soundings launched from the network of radiosonde stations involved in the DTS-MEDEX-2009 campaign

Ventricular Tachycardia and Heart Failure

Ventricular tachycardia (VT) is a common arrhythmia seen in patients with heart failure (HF) and is now seen more frequently as these patients survive longer with modern therapies. In patients with HF, half of the deaths are sudden due to life-threatening ventricular arrhythmias, including VT. Although disease modifying drugs, such as beta blockers, mineralocorticoid drugs, and angiotensin receptor neprilysin inhibitors, prevent the occurrence of VT to some extent, the mainstay of therapy is the antiarrhythmic drug therapy, implantable cardioverter-defibrillator (ICD) implantation, and traditional radiofrequency catheter ablation. Autonomic nerve system modulation and stereotactic body radiation therapy have emerged as novel techniques for the management of refractory VT cases. Patients with refractory VT and repetitive ICD shocks should be further evaluated regarding the candidacy for left ventricular assist device and transplantation

Timing-Constrained Global Routing with Buffered Steiner Trees

This dissertation deals with the combination of two key problems that arise in the physical design of computer chips: global routing and buffering. The task of buffering is the insertion of buffers and inverters into the chip's netlist to speed-up signal delays and to improve electrical properties of the chip. Insertion of buffers and inverters goes alongside with construction of Steiner trees that connect logical sources with possibly many logical sinks and have buffers and inverters as parts of these connections. Classical global routing focuses on packing Steiner trees within the limited routing space. Buffering and global routing have been solved separately in the past. In this thesis we overcome the limitations of the classical approaches by considering the buffering problem as a global, multi-objective problem. We study its theoretical aspects and propose algorithms which we implement in the tool BonnRouteBuffer for timing-constrained global routing with buffered Steiner trees. At its core, we propose a new theoretically founded framework to model timing constraints inherently within global routing. As most important sub-task we have to compute a buffered Steiner tree for a single net minimizing the sum of prices for delays, routing congestion, placement congestion, power consumption, and net length. For this sub-task we present a fully polynomial time approximation scheme to compute an almost-cheapest Steiner tree with a given routing topology and prove that an exact algorithm cannot exist unless P=NP. For topology computation we present a bicriteria approximation algorithm that bounds both the geometric length and the worst slack of the topology. To improve the practical results we present many heuristic modifications, speed-up- and post-optimization techniques for buffered Steiner trees. We conduct experiments on challenging real-world test cases provided by our cooperation partner IBM to demonstrate the quality of our tool. Our new algorithm could produce better solutions with respect to both timing and routability. After post-processing with gate sizing and Vt-assignment, we can even reduce the power consumption on most instances. Overall, our results show that our tool BonnRouteBuffer for timing-constrained global routing is superior to industrial state-of-the-art tools

Timing-Constrained Global Routing with RC-Aware Steiner Trees and Routing Based Optimization

In this thesis we consider the global routing problem, which arises as one of the major subproblems in the physical design step in VLSI design. In global routing, we are given a three-dimensional grid graph G with edge capacities representing available routing space, and we have to connect a set of nets in G without overusing any edge capacities. Here, each net consists of a set of pins corresponding to vertices of G, where one pin is the sender of signals, while all other pins are receivers. Traditionally, next to obeying all edge capacity constraints, the objective has been to minimize wire length and possibly via (edges in z-direction) count, and timing constraints on the chip were only modeled indirectly. We present a new approach, where timing constraints are modeled directly during global routing: In joint work with Stephan Held, Dirk Mueller, Daniel Rotter, Vera Traub and Jens Vygen, we extend the modeling of global routing as a Min-Max Resource Sharing Problem to also incorporate timing constraints. For measuring signal delays we use the well-established Elmore delay model. One of the key subproblems here is the computation of Steiner trees minimizing a weighted sum of routing space usages and signal delays. For k pins, this problem is NP-hard to approximate within o(log k), and even the special case k = 2 is NP-hard, as was shown by Haehnle and Rotter. We present a fast approximation algorithm with strong approximation bounds for the case k = 2. For k > 2 we use a multi-stage approach based on modifying the topology of a short Steiner tree and using our algorithm for the two-pin case for computing new connections. Moreover, we present a layer assignment algorithm that assigns z-coordinates to the edges of a given two-dimensional tree. We also discuss the topic of routing based optimization. Here, the starting point is a complete routing, and timing optimization tools make changes that require incremental adaptations of the underlying routing. We investigate several aspects of this problem and derive a new routing flow that includes our timing-aware global router and routing based optimization steps. We evaluate our results from this thesis in practice on industrial 14nm microprocessor designs from IBM. Our theoretical results are validated in practice by a strong performance of our timing-aware global routing framework and our new routing flow, yielding significant improvements over the traditional global routing method and the previously used routing flow. Therefore, we conclude that our approaches and results from this thesis are not only theoretically sound but also give compelling results in practice

The Northern Sky Optical Cluster Survey IV: An Intermediate Redshift Galaxy Cluster Catalog and the Comparison of Two Detection Algorithms

We present an optically selected galaxy cluster catalog from ~ 2,700 square degrees of the Digitized Second Palomar Observatory Sky Survey (DPOSS), spanning the redshift range 0.1 < z < 0.5, providing an intermediate redshift supplement to the previous DPOSS cluster survey. This new catalog contains 9,956 cluster candidates and is the largest resource of rich clusters in this redshift range to date. The candidates are detected using the best DPOSS plates based on seeing and limiting magnitude. The search is further restricted to high galactic latitude (|b| > 50), where stellar contamination is modest and nearly uniform. We also present a performance comparison of two different detection methods applied to this data, the Adaptive Kernel and Voronoi Tessellation techniques. In the regime where both catalogs are expected to be complete, we find excellent agreement, as well as with the most recent surveys in the literature. Extensive simulations are performed and applied to the two different methods, indicating a contamination rate of ~ 5%. These simulations are also used to optimize the algorithms and evaluate the selection function for the final cluster catalog. Redshift and richness estimates are also provided, making possible the selection of subsamples for future studies.Comment: 64 pages, 32 figures. Accepted to AJ; appearing in September. Version with full resolution figures is available at http://www.astro.caltech.edu/~paal/paper/NoSOCS_IV.ps.g