Circuit designers perform optimization procedures targeting speed and power
during the design of a circuit. Gate sizing can be applied to optimize for speed, while
Dual-VT and Dynamic Voltage Scaling (DVS) can be applied to optimize for leakage
and dynamic power, respectively. Both gate sizing and Dual-VT are design-time
techniques, which are applied to the circuit at a fixed voltage. On the other hand, DVS
is a run-time technique and implies that the circuit will be operating at a different voltage
than that used during the optimization phase at design-time. After some analysis, the
risk of non-critical paths becoming critical paths at run-time is detected under these
circumstances. The following questions arise: 1) should we take DVS into account
during the optimization phase? 2) Does DVS impose any restrictions while performing
design-time circuit optimizations?. This thesis is a case study of applying DVS to a
circuit that has been optimized for speed and power, and aims at answering the previous
two questions.
We used a 45-nm CMOS design kit and flow. Synthesis, placement and routing,
and timing analysis were applied to the benchmark circuit ISCAS?85 c432. Logical
Effort and Dual-VT algorithms were implemented and applied to the circuit to optimize for speed and leakage power, respectively. Optimizations were run for the circuit
operating at different voltages. Finally, the impact of DVS on circuit optimization was
studied based on HSPICE simulations sweeping the supply voltage for each
optimization.
The results showed that DVS had no impact on gate sizing optimizations, but it
did on Dual-VT optimizations. It is shown that we should not optimize at an arbitrary
voltage. Moreover, simulations showed that Dual-VT optimizations should be performed
at the lowest voltage that DVS is intended to operate, otherwise non-critical paths will
become critical paths at run-time
