Proceedings of the Cold Electronics Workshop

The benefits and problems of the use of cold semiconductor electronics and the research and development effort required to bring cold electronics into more widespread use were examined

Fabrication and characterisation of novel Ge MOSFETs

As high-k dielectrics are introduced into commercial Si CMOS (Complimentary Metal Oxide Semiconductor) microelectronics, the 40 year channel/dielectric partnership of Si/SiO2 is ended and the door opened for silicon to be replaced as the active channel material in MOSFETs (Metal Oxide Semiconductor Field Effect Transistor). Germanium is a good candidate as it has higher bulk carrier mobilities than silicon. In addition, Si and Ge form a thermodynamically stable SiGe alloy of any composition, allowing Ge to be implemented as a thin layer on the surface of a standard Si substrate. This thesis is a practical investigation on several aspects of Ge CMOS technology. High-k dielectric Ge p-MOSFETs are electrically characterised. A large variation in interface state densities is demonstrated to be responsible for a threshold voltage shift and this is proportional to reciprocal peak mobility due to the Coulomb scattering of carriers by charged states. A theoretical mobility is fitted to that measured at 4.2 K and confirms that interface states are the main source of interface charged impurities. The model demonstrates a reduction in the interface charged impurity density in p-MOSFETs that underwent a PMA (Post Metallisation Anneal) in hydrogen atmosphere and that the anneal also reduces the RMS (Root Mean Square) dielectric/semiconductor interface roughness, from an average of 0.60 nm to 0.48 nm. High-k strained Ge p-MOSFETs are electrically characterised and have peak mobilities at 300 K (470 cm2 V-1 s-1) and 4.2 K (1780 cm2 V-1 s-1) far in excess of those measured for the unstrained Ge p-MOSFETs (285 cm2 V-1 s-1,785 cm2 V-1 s-1 respectively). Strained Ge n-MOSFETs perform significantly worse than standard Si P, - MOSFETs primarily due to a high source/drain resistance. A 10 nm thick SiGe-01 (On Insulator) layer with a Ge composition of 58% is obtained from a 55 nm Si0_88Ge1o2. initial layer on 100 nm Si-Ol substrate via the germanium condensation technique. For the first time, germanium is demonstrated to diffuse through the BOX (Buried OXide) during Ge-condensation and into the underlying Si substrate. An order of magnitude increase in the calculated ITOX (Internal Thermal OXidation) rate of the BOX in the final stages of Ge-condensation is hypothesised to be responsible for stopping this diffusion

Development of room temperature operating single electron transistor using FIB etching and deposition technology

The single-electron transistor (SET) is one of the best candidates for future nano electronic circuits because of its ultralow power consumption, small size and unique functionality. SET devices operate on the principle of Coulomb blockade, which is more prominent at dimensions of a few nano meters. Typically, the SET device consists of two capacitively coupled ultra-small tunnel junctions with a nano island between them. In order to observe the Coulomb blockade effects in a SET device the charging energy of the device has to be greater that the thermal energy. This condition limits the operation of most of the existing SET devices to cryogenic temperatures. Room temperature operation of SET devices requires sub-10nm nano-islands due to the inverse dependence of charging energy on the radius of the conducting nano-island. Fabrication of sub-10nm structures using lithography processes is still a technological challenge. In the present investigation, Focused Ion Beam based etch and deposition technology is used to fabricate single electron transistors devices operating at room temperature. The SET device incorporates an array of tungsten nano-islands with an average diameter of 8nm. The fabricated devices are characterized at room temperature and clear Coulomb blockade and Coulomb oscillations are observed. An improvement in the resolution limitation of the FIB etching process is demonstrated by optimizing the thickness of the active layer. SET devices with structural and topological variation are developed to explore their impact on the behavior of the device. The threshold voltage of the device was minimized to ~500mV by minimizing the source-drain gap of the device to 17nm. Vertical source and drain terminals are fabricated to realize single-dot based SET device. A unique process flow is developed to fabricate Si dot based SET devices for better gate controllability in the device characteristic. The device vi parameters of the fabricated devices are extracted by using a conductance model. Finally, characteristic of these devices are validated with the simulated data from theoretical modeling

Fabrication and characterisation of novel Ge MOSFETs

As high-k dielectrics are introduced into commercial Si CMOS (Complimentary Metal Oxide Semiconductor) microelectronics, the 40 year channel/dielectric partnership of Si/SiO2 is ended and the door opened for silicon to be replaced as the active channel material in MOSFETs (Metal Oxide Semiconductor Field Effect Transistor). Germanium is a good candidate as it has higher bulk carrier mobilities than silicon. In addition, Si and Ge form a thermodynamically stable SiGe alloy of any composition, allowing Ge to be implemented as a thin layer on the surface of a standard Si substrate. This thesis is a practical investigation on several aspects of Ge CMOS technology. High-k dielectric Ge p-MOSFETs are electrically characterised. A large variation in interface state densities is demonstrated to be responsible for a threshold voltage shift and this is proportional to reciprocal peak mobility due to the Coulomb scattering of carriers by charged states. A theoretical mobility is fitted to that measured at 4.2 K and confirms that interface states are the main source of interface charged impurities. The model demonstrates a reduction in the interface charged impurity density in p-MOSFETs that underwent a PMA (Post Metallisation Anneal) in hydrogen atmosphere and that the anneal also reduces the RMS (Root Mean Square) dielectric/semiconductor interface roughness, from an average of 0.60 nm to 0.48 nm. High-k strained Ge p-MOSFETs are electrically characterised and have peak mobilities at 300 K (470 cm2 V-1 s-1) and 4.2 K (1780 cm2 V-1 s-1) far in excess of those measured for the unstrained Ge p-MOSFETs (285 cm2 V-1 s-1,785 cm2 V-1 s-1 respectively). Strained Ge n-MOSFETs perform significantly worse than standard Si P, - MOSFETs primarily due to a high source/drain resistance. A 10 nm thick SiGe-01 (On Insulator) layer with a Ge composition of 58% is obtained from a 55 nm Si0_88Ge1o2. initial layer on 100 nm Si-Ol substrate via the germanium condensation technique. For the first time, germanium is demonstrated to diffuse through the BOX (Buried OXide) during Ge-condensation and into the underlying Si substrate. An order of magnitude increase in the calculated ITOX (Internal Thermal OXidation) rate of the BOX in the final stages of Ge-condensation is hypothesised to be responsible for stopping this diffusion.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Molecular Beam Epitaxy of Narrow Gap Quantum Wells: InSb, InGaAs and Elemental Sb

In this work the electronic properties of n-type and p-type quantum wells (QWs) made of narrow gap InSb and InGaAs materials have been studied experimentally. The narrower band gap in these materials leads to smaller effective masses for electrons and holes, therefore higher mobilities are expected. High intrinsic electron mobility due to the small effective mass for electrons in these materials makes them attractive as the channel material in n-type transistors. The layer structure, doping and growth parameters were further optimized to enhance the mobility for electrons in InSb and InGaAs QWs. A room-temperature electron mobility of 11,600cm2/Vs and 44,700cm2/Vs were achieved in our QWs made of In0.64Ga0.36As and InSb, respectively.The hole effective mass in InSb QWs with different strain and confinement was studied. To achieve high hole mobilities, strain and confinement must be maximized. Both parameters increase the energy splitting between heavy and light hole bands and lower the effective mass for in-plane motion. The smallest hole effective mass of 0.017me was observed in an InSb QW with 1.05% strain and 7nm well width. Hole mobility in strained InSb QWs grown on GaAs(001) substrates can be significantly improved by better buffer layer design. The effect of the thickness and the Al composition in the Alxln1-xSb initial buffer layer on hole mobility of p-type InSb QWs was also studied. A room-temperature hole mobility of 1,050cm2/Vs has been achieved in our improved p-type InSb QW with 1.32% strain, 7nm well width and a 0.8μm thick Al0.15In0.85Sb initial buffer layer. The compressive strain was introduced into InyGa1-yAs QWs by increasing the Indium composition (y) in the well slightly above the value needed for lattice matching (y=0.53) with InP (001) substrates. A room temperature hole mobility of 230cm2/Vs was obtained in our In0.75Ga0.25As QW with remotely, Be delta-doped In0.45Al0.55As barrier layers.An experimental study of growth, structural and electronic properties of elemental Sb QWs with GaSb barriers was performed to explore their potential as topological insulators. Molecular beam epitaxy growth procedures on GaAs(111)A and GaSb(111)A were developed to realize ultra-thin layers of Sb with a thickness ≤ 4nm. Transmission electron microscopy and scanning electron microscopy indicated good crystalline quality in these ultra-thin layers of Sb. Resistivity measurements indicated that Sb QWs with a thickness above ~2nm were metallic, whereas thinner wells showed insulating behavior

Hot-carrier reliability of MOSFETs at room and cryogenic temperature

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.Vita.Includes bibliographical references.Hot-carrier reliability is an increasingly important issue as the geometry scaling of MOSFET continues down to the sub-quarter micron regime. The power-supply voltage does not scale at the same rate as the device dimensions, and thus, the peak lateral E-field in the channel increases. Hot-carriers, generated by this high lateral E-field, gain more kinetic energy and cause damage to the device as the geometry dimension of MOSFETs shortens. In order to model the device hot-carrier degradation accurately, accurate model parameter extraction is critically important. This thesis discusses the model parameters' dependence on the stress conditions and its implications in terms of the device lifetime prediction procedure. As geometry scaling approaches the physical limit of fabrication techniques, such as photolithography, temperature scaling becomes a more viable alternative. MOSFET performance enhancement has been investigated and verified at cryogenic temperatures, such as at 77K. However, hot-carrier reliability problems have been shown to be exacerbated at low temperature. As the mean-free path increases at low temperature due to reduced phonon-scattering, hot-carriers become more energetic at low temperature, causing more device degradation. It is clear that various hot-carrier reliability issues must be clearly understood in order to optimize the device performance vs. reliability trade-off, both at short channel lengths and low temperatures. This thesis resolves numerous, unresolved issues of hot-carrier reliability at both room and cryogenic temperature, and develops a general framework for hot carrier reliability assessment.by SeokWon Abraham Kim.Ph.D