10 research outputs found

    Time and Cost Optimization of Cyber-Physical Systems by Distributed Reachability Analysis

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    Refinement of communication and states in models of embedded systems

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    This thesis addresses two particular issues related to the design of embedded systems; namely, refinement of communication and refinement of states. The refinement of communication deals with the issue of implementing a synchronous system in an asynchronous way such that two systems are behaviourally equivalent. As a result, correctness of an asynchronous system can be achieved by establishing correctness on its synchronous version, which is computationally cheaper than analysing the latter. The research objective was to find conditions that ensure the addition of buffers do not modify the behaviour of a given synchronous system. We show that it is possible to obtain better desynchronisability conditions (even for finer equivalence like branching bisimulation) by changing the properties of the communication protocol. This is in contrast with the previous works where the focus was only on restricting the communicating components. The refinement of states deals with the stepwise development of hybrid systems. Such a concept was absent in the Compositional Interchange Format (CIF), a modelling language for embedded systems based on hybrid automata and some process algebraic operators. The research objective was to develop a compositional operational semantics of CIF with hierarchy (HCIF). We show that by referring only to the transition system of the substructures (not to their syntactic representation), the semantics of HCIF operators is almost unchanged with respect to their CIF versions. Furthermore, a definition to eliminate hierarchy in a HCIF model is presented. As a result, the existing simulation tools and the transformation tools to other timed or hybrid languages can be reused upon the elimination of hierarchy from a HCIF model

    Model Checking and Model-Based Testing : Improving Their Feasibility by Lazy Techniques, Parallelization, and Other Optimizations

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    This thesis focuses on the lightweight formal method of model-based testing for checking safety properties, and derives a new and more feasible approach. For liveness properties, dynamic testing is impossible, so feasibility is increased by specializing on an important class of properties, livelock freedom, and deriving a more feasible model checking algorithm for it. All mentioned improvements are substantiated by experiments

    Computer Aided Verification

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    The open access two-volume set LNCS 12224 and 12225 constitutes the refereed proceedings of the 32st International Conference on Computer Aided Verification, CAV 2020, held in Los Angeles, CA, USA, in July 2020.* The 43 full papers presented together with 18 tool papers and 4 case studies, were carefully reviewed and selected from 240 submissions. The papers were organized in the following topical sections: Part I: AI verification; blockchain and Security; Concurrency; hardware verification and decision procedures; and hybrid and dynamic systems. Part II: model checking; software verification; stochastic systems; and synthesis. *The conference was held virtually due to the COVID-19 pandemic

    Fundamental Approaches to Software Engineering

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    This open access book constitutes the proceedings of the 23rd International Conference on Fundamental Approaches to Software Engineering, FASE 2020, which took place in Dublin, Ireland, in April 2020, and was held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020. The 23 full papers, 1 tool paper and 6 testing competition papers presented in this volume were carefully reviewed and selected from 81 submissions. The papers cover topics such as requirements engineering, software architectures, specification, software quality, validation, verification of functional and non-functional properties, model-driven development and model transformation, software processes, security and software evolution

    Verifying liveness in supervised systems using UPPAAL and mCRL2

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    Supervisory control ensures safe coordination of high-level discrete-event system behavior. Supervisory controllers observe discrete-event system behavior, make a decision on allowed activities, and communicate the control signals to the involved parties. Models of such controllers are automatically synthesized from the formal models of the unsupervised system and the specified safety requirements. Traditionally, the supervisory controllers do not ensure that intended behavior is preserved, but only ensure that undersired behavior is precluded. Recent work suggested that ensuring liveness properties during the synthesis procedure is a costly undertaking. Therefore, we augment state-of-the-art synthesis tools to provide for efficient post-synthesis verification. To this end, we interface a model-based systems engineering framework with the state-based model checker UPPAAL and the event-based tool suite mCRL2. We demonstrate the framework on an industrial case study involving coordination of maintenance procedures of a high-end printer. Based on our experiences, we discuss the advantages and disadvantages of the used tools. A comparison is given of the functionality offered by the tools and the extent to which these are useful in our proposed method

    Verifying liveness in supervised systems using UPPAAL and mCRL2

    No full text
    Supervisory control ensures safe coordination of high-level discrete-event system behavior. Supervisory controllers observe discrete-event system behavior, make a decision on allowed activities, and communicate the control signals to the involved parties. Models of such controllers are automatically synthesized from the formal models of the unsupervised system and the specified safety requirements. Traditionally, the supervisory controllers do not ensure that intended behavior is preserved, but only ensure that undersired behavior is precluded. Recent work suggested that ensuring liveness properties during the synthesis procedure is a costly undertaking. Therefore, we augment state-of-the-art synthesis tools to provide for efficient post-synthesis verification. To this end, we interface a model-based systems engineering framework with the state-based model checker UPPAAL and the event-based tool suite mCRL2. We demonstrate the framework on an industrial case study involving coordination of maintenance procedures of a high-end printer. Based on our experiences, we discuss the advantages and disadvantages of the used tools. A comparison is given of the functionality offered by the tools and the extent to which these are useful in our proposed method
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