String Parton Models in Geant4

Dual parton and quark gluon string model are the by now almost standard theoretical techniques by which one can arrive at precision description of high energy, soft, inclusive reactions. These reactions make the part of jets at energies that contribute strongly to discovery channels such as H$\to$WWjj, or search for compositeness at the highest transverse momenta. The above modeling approach is available with Geant4 for nucleon induced reactions since the first release. Its object oriented design and parameter set was recently extended to allow for simulation of pion and kaon induced reactions, as well as heavy ion reactions. We will briefly describe the theory and algorithmic approaches that underly the modeling, show the object oriented designs and component structure of the string parton sub-systems of Geant4, present validation/verification results pertaining to these models, as well as results concerning their usage in calorimeter simulation.Comment: Computing in High Energy and Nuclear Physics, La Jolla, California, March 24-28, 2003 1 tar fil

A framework for system level verification : the SystemC Case

Recent advances in hardware design has enabled integration of a complete yet complex systems on a single chip (called System-on-a-Chip: SoC). It is conceivable that the role of traditional Register Transfer level (RTL) languages will diminish to an extent akin to assembly level languages in software design. Therefore, new design languages or so-called System Level Languages (SLL) have emerged. Verification techniques for SOC designs also need to change with this trend. Combining classical verification techniques, such as simulation, with several other formal techniques, into a single approach has been gaining attention in SoC verification. Classical simulation based verification techniques when used with SystemC face several problems related to the object-oriented aspect of SystemClibrary and due to the complexity of its simulation environment. In this talk, we present our proposed methodology to verify SoC designs modeled in SystemC. To this end, we introduce a hybrid approach combining static code analysis, model checking and assertion based verification. We also propose to augment the approach by a test generation module in order to improve the coverage metrics in comparison to the classical simulation approach (mainly based on random test generation

Building Blocks for Control System Software

Software implementation of control laws for industrial systems seem straightforward, but is not. The computer code stemming from the control laws is mostly not more than 10 to 30% of the total. A building-block approach for embedded control system development is advocated to enable a fast and efficient software design process.\ud We have developed the CTJ library, Communicating Threads for Java¿,\ud resulting in fundamental elements for creating building blocks to implement communication using channels. Due to the simulate-ability, our building block method is suitable for a concurrent engineering design approach. Furthermore, via a stepwise refinement process, using verification by simulation, the implementation trajectory can be done efficiently

An overview of very high level software design methods

Very High Level design methods emphasize automatic transfer of requirements to formal design specifications, and/or may concentrate on automatic transformation of formal design specifications that include some semantic information of the system into machine executable form. Very high level design methods range from general domain independent methods to approaches implementable for specific applications or domains. Applying AI techniques, abstract programming methods, domain heuristics, software engineering tools, library-based programming and other methods different approaches for higher level software design are being developed. Though one finds that a given approach does not always fall exactly in any specific class, this paper provides a classification for very high level design methods including examples for each class. These methods are analyzed and compared based on their basic approaches, strengths and feasibility for future expansion toward automatic development of software systems

A framework of web-based conceptual design

A web-based conceptual design prototype system is presented. The system consists of four parts which interpret on-line sketches as 2D and 3D geometry, extract 3D hierarchical configurations, allow editing of component behaviours, and produce VRML-based behavioural simulations for design verification and web-based application. In the first part, on-line freehand sketched input is interpreted as 2D and 3D geometry, which geometrically represents conceptual design. The system then infers 3D configuration by analysing 3D modelling history. The configuration is described by a parent–child hierarchical relationship and relative positions between two geometric components. The positioning information is computed with respect to the VRML97 specification. In order to verify the conceptual design of a product, the behaviours can be specified interactively on different components. Finally, the system creates VRML97 formatted files for behavioural simulation and collaborative design application over the Internet. The paper gives examples of web-based applications. This work forms a part of a research project into the design and establishing of modular machines for automation manufacture. A consortium of leading automotive companies is collaborating on the research project

IEEE Standard 1500 Compliance Verification for Embedded Cores

Core-based design and reuse are the two key elements for an efficient system-on-chip (SoC) development. Unfortunately, they also introduce new challenges in SoC testing, such as core test reuse and the need of a common test infrastructure working with cores originating from different vendors. The IEEE 1500 Standard for Embedded Core Testing addresses these issues by proposing a flexible hardware test wrapper architecture for embedded cores, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Several intellectual property providers have already announced IEEE Standard 1500 compliance in both existing and future design blocks. In this paper, we address the problem of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE Standard 1500. This step is mandatory to fully trust the wrapper functionalities in applying the test sequences to the core. We present a systematic methodology to build a verification framework for IEEE Standard 1500 compliant cores, allowing core providers and/or integrators to verify the compliance of their products (sold or purchased) to the standar

On the Transformation of SystemC to AsmL Using Abstract Interpretation

SystemC is among a group of system level design languages proposed to raise the abstraction level for embedded system design and verification. A straight and sound verification by model checking or theorem proving of SystemC designs is, however, infeasible given the object-oriented nature of this library and the complexity of its simulation environment. We illustrated, in a previous work, the feasibility and success of performing model checking and assertions monitors generation of SystemC using a variant of Abstract State Machines (ASM) languages (AsmL). In this paper, we establish the soundness of our approach by proving the correctness of the transformation from SystemC to AsmL

A CSP-Based Trajectory for Designing Formally Verified Embedded Control Software

This paper presents in a nutshell a procedure for producing formally verified concurrent software. The design paradigm provides means for translating block-diagrammed models of systems from various problem domains in a graphical notation for process-oriented architectures. Briefly presented CASE tool allows code generation both for formal analysis of the models of software and code generation in a target implementation language. For formal analysis a highquality commercial formal checker is used