Memristor-based Random Access Memory: The delayed switching effect could revolutionize memory design

Memristor’s on/off resistance can naturally store binary bits for non-volatile memories. In this work, we found that memristor’s another peculiar feature that the switching takes place with a time delay (we name it “the delayed switching”) can be used to selectively address any desired memory cell in a crossbar array. The analysis shows this is a must-be in a memristor with a piecewise-linear ?-q curve. A “circuit model”-based experiment has verified the delayed switching feature. It is demonstrated that memristors can be packed at least twice as densely as semiconductors, achieving a significant breakthrough in storage density

High-Precision Tuning of State for Memristive Devices by Adaptable Variation-Tolerant Algorithm

Using memristive properties common for the titanium dioxide thin film devices, we designed a simple write algorithm to tune device conductance at a specific bias point to 1% relative accuracy (which is roughly equivalent to 7-bit precision) within its dynamic range even in the presence of large variations in switching behavior. The high precision state is nonvolatile and the results are likely to be sustained for nanoscale memristive devices because of the inherent filamentary nature of the resistive switching. The proposed functionality of memristive devices is especially attractive for analog computing with low precision data. As one representative example we demonstrate hybrid circuitry consisting of CMOS summing amplifier and two memristive devices to perform analog multiply and accumulate computation, which is a typical bottleneck operation in information processing.Comment: 20 pages, 6 figure

Filamentary extension of the mem-con theory of memristance and its application to titanium dioxide sol-gel memristors

Titanium dioxide sol-gel memristors have two different modes of operation, believed to be dependent on whether there is bulk memristance, i.e. memristance throughout the whole volume or filamentary memristance, i.e. memristance caused by the connection of conducting filaments. The mem-con theory of memristance is based on the drift of oxygen vacancies rather than that of conducting electrons and has been previously used to describe bulk memristance in several devices. Here, the mem-con theory is extended to model memristance caused by small filaments of low resistance titanium dioxide and it compares favorably to experimental results for filamentary memristance in sol-gel devices

Logaritmik Memristanslı TiO2 Memristör

An ideal memristor, which was claimed to be the fourth fundamental element of circuit design by Dr. Chua in 1971, is a nonlinear resistor and its properties cannot be mimicked with linear time-invariant circuit elements. A thin-film which behaves as if a memristor has been declared found experimentally by a HP research team lead by Stanley Williams in 2008. A quite explicit model of the memristor has also been given by the team. The HP memristor resistance can be found by summing the resistances of the doped and undoped regions. Assuming the doped region length is proportional to memristor charge, which is the integration of memristor current, the doped region has a constant drift speed, and a constant memristor cross-section, the HP memristor resistance has a linear charge dependency till it saturates. In this paper, it is shown that a memristor with a logarithmic charge dependency can be made using the principles given by the team and making some modifications to memristor geometry.İdeal bir memristör, 1971 yılında Dr. Chua tarafından devre tasarımı için dördüncü temel devre elemanı olarak iddia edilen nonlinear bir dirençtir ve özellikleri lineer zamanla-değişmeyen devre elemanları tarafından taklit edilememektedir. Memristör olarak davranan bir ince-filmin bulunduğu, 2008 senesinde Stanley Williams tarafından yönetilen bir HP araştırma timi tarafından ilan edilmiştir. Bu memristörün oldukça anlaşılabilir bir modeli de bu tim tarafından verilmiştir. Bu HP memristör direnci katkılanmış ve katkılanmamış bölgelerin dirençlerini ekleyerek bulunabilir. Katkılanmış bölge uzunluğunun akımın integrali olan memristör yüküne orantılı olduğu, katkılanmış bölgenin sabit bir sürüklenme hızına sahip olduğu ve memristör kesiti sabit olarak kabul edilirek, HP memristör direncinin, doyma gerçekleşene kadar, lineer yük bağımlılığı vardır. Bu makalede, logaritmik yük bağımlılığı olan bir memristörün HP timi tarafından verilen prensipleri kullanarak ve memristör geometrisine bazı değişiklikler yapılarak yapılabileceği gösterilmiştir

Memristors: a short review on fundamentals, structures, materials and applications

The paper contains a short literature review on the subject of special type of thin film structures with resistive-switching memory effect. In the literature, such structures are commonly labeled as "memristors". The word "memristor" originates from two words: "memory" and "resistor". For the first time, the memristor was theoretically described in 1971 by Leon Chua as the 4th fundamental passive electronics element with a non-linear current-voltage behavior. The reported area of potential usage of memristor is enormous. It is predicted that the memristor could find application, for example in the domain of nonvolatile random access memory, flash memory, neuromorphic systems and so forth. However, in spite of the fact that plenty of papers have been published in the subject literature to date, the memristor still behaves as a "mysterious" electronic element. It seems that, one of the important reasons that such structures are not yet in practical use, is unsufficient knowledge of physical phenomena determining occurrence of the switching effect. The present paper contains a literature review of available descriptions of theoretical basis of the memristor structures, used materials, structure configurations and discussion about future prospects and limitations

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor