A Fully Polynomial-Time Approximation Scheme for Speed Scaling with Sleep State

We study classical deadline-based preemptive scheduling of tasks in a computing environment equipped with both dynamic speed scaling and sleep state capabilities: Each task is specified by a release time, a deadline and a processing volume, and has to be scheduled on a single, speed-scalable processor that is supplied with a sleep state. In the sleep state, the processor consumes no energy, but a constant wake-up cost is required to transition back to the active state. In contrast to speed scaling alone, the addition of a sleep state makes it sometimes beneficial to accelerate the processing of tasks in order to transition the processor to the sleep state for longer amounts of time and incur further energy savings. The goal is to output a feasible schedule that minimizes the energy consumption. Since the introduction of the problem by Irani et al. [16], its exact computational complexity has been repeatedly posed as an open question (see e.g. [2,8,15]). The currently best known upper and lower bounds are a 4/3-approximation algorithm and NP-hardness due to [2] and [2,17], respectively. We close the aforementioned gap between the upper and lower bound on the computational complexity of speed scaling with sleep state by presenting a fully polynomial-time approximation scheme for the problem. The scheme is based on a transformation to a non-preemptive variant of the problem, and a discretization that exploits a carefully defined lexicographical ordering among schedules

Techniques to Save Energy in Heterogeneous Multicore Architectures under QoS Constraints

Typically, applications are run with available system resources leading to over-provisioning of resources which can lead to high energy consumption. If the computational demand is specified, in terms of a Quality of Service\ua0(QoS) contract, it is possible to devote just enough resources to applications\ua0and thereby reduce energy consumption. Modern heterogeneous multicore\ua0platforms, such as ARM big.LITTLE, typically provide a multidimensional\ua0space of resources, called configuration space, such as Voltage-Frequency (V-F)\ua0settings, thread count and processor types, which can be configured at run-time\ua0to open up new opportunities for resource management.\ua0This thesis presents techniques to improve energy efficiency under the constraint of QoS by managing the resource allocation at run-time for applications\ua0run on heterogeneous multicore platforms. The applications considered are iterative with a computational deadline associated with each loop iteration.\ua0The proposed techniques apply to a framework that uses applications’ outer loop iterations as a means for progress-tracking and prediction of the execution time.A first contribution of the thesis is a resource management technique for single-threaded applications that uses core type (e.g. big or little cores) and\ua0V-F settings as a configuration space to select a configuration, for each iteration,\ua0based on the execution-time prediction of future iterations and computational\ua0deadlines. The thesis shows that an energy saving of 25% over the race-to-idle\ua0state-of-the-art technique is achieved without missing any deadlines. This\ua0scheme incurs only 0.6% and 0.8% of timing and energy overheads, respectively.\ua0A second contribution of the thesis is a novel resource-management policy\ua0for multi-threaded applications. Here, the configuration space is extended to\ua0also consider the thread count, i.e., the number of cores assigned to multi-threaded applications. The proposed technique first chooses the most energy-efficient configuration that meets the computational deadline. Since an iteration\ua0typically finishes before the deadline, the proposed technique collects the\ua0generated execution-time slack over subsequent iterations with the goal of\ua0selecting a configuration that can save more energy. To allow for on-line exploration of the configuration space, at low overhead, a third contribution of\ua0the thesis is an online, low-overhead prediction method based on interpolation,\ua0that measures the execution statistics at end points of each configuration-space\ua0dimension and interpolates the values at intermediate configurations. Overall,\ua0the proposed technique saves 61% energy compared to the state-of-the-artrace-to-idle technique without missing any deadlines. Further, it only incurs\ua00.6% and 0.7% of timing and energy overheads, respectively

A Fully Polynomial-Time Approximation Scheme for Speed Scaling with Sleep State

International audienc

Thermal Management of Electronics and Optoelectronics: From Heat Source Characterization to Heat Mitigation at the Device and Package Levels

Thermal management of electronic and optoelectronic devices has become increasingly challenging. For electronic devices, the challenge arises primarily from the drive for miniaturized, high-performance devices, leading to escalating power density. For optoelectronics, the recent widespread use of organic light emitting diode (OLED) displays in mobile platforms and flexible electronics presents new challenges for heat dissipation. Furthermore, the performance and reliability of increasingly high-power semiconductor lasers used for telecommunications and other applications hinge on proper thermal management. For example, small, concentrated hotspots may trigger thermal runaway and premature device destruction. Emerging challenges in thermal management of devices require innovative methods to characterize and mitigate heat generation and temperature rise at the device level as well as the package level. The first part of this dissertation discusses device-level thermal management. A thermal imaging microscope with high spatial resolution (~450nm) is created for hotspot detection in the context of diode lasers under back-irradiance (BI). Laser facet temperature maps reveal the existence of a critical BI spot location that increases the laser’s active region temperature by nearly a factor of 3. An active solid-state cooling strategy that could scale down to the size of hotspots in modern devices is then explored, utilizing energy filtering at carbon nanotube (CNT) junctions as a means to provide thermionic cooling at nanometer spatial scales. The CNT cooler exhibits a large effective Seebeck coefficient of 386μV/K and a relatively moderate thermal conductivity, together giving rise to a high cooling capacity (2.3 × 106 W/cm2). Thermal management at the package level is then considered. Heat transfer in polymers is first studied, owing to their prevalence in thermal interface materials as well as organic devices (e.g., OLEDs). Employing molecular design principles developed to engineer the thermal properties of polymers, molecular-scale electrostatic repulsive forces are utilized to modify chain morphologies in amorphous polymers, leading to spin-cast films that are free of ceramic or metallic fillers yet have thermal conductivities as high as 1.17 Wm-1K-1, which is approximately 6 times that of typical amorphous polymers. Electronics packaging designs incorporating phase change materials (PCMs) are then considered as a means to mitigate bursty heat sources; PCM incorporation in a packaged accelerator chip intended for large-scale object identification is found to suppress the peak die temperature by 17%.PHDMechanical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/150013/1/chenlium_1.pd