Comparison of Conventional and Maskless Lithographic Techniques for More than Moore Post-processing of Foundry CMOS Chips

This article details and compares the technology options for post-processing foundry produced CMOS at chip-scale to enable More than Moore functionality. In many cases there are attractions in using chip-based processing through the Multi-Project Wafer route that is frequently employed in research, early-stage development and low-volume production. This article identifies that spray-based photoresist deposition combined with optical maskless lithography demonstrates sufficient performance combined with low cost and operational convenience to offer an attractive alternative to conventional optical lithography, where spin-coated photoresist is exposed through a patterned photomask. [2020-0249

From Lab-on-chip to Lab-in-App: Challenges towards silicon photonic biosensors product developments

This work presents and evaluates different approaches of integrated optical sensors based on photonic integrated circuit (PIC) technologies for refractive index sensing. Bottlenecks in the fabrication flow towards an applicable system are discussed that hinder a cost-effective mass-production for disposable sensor chips. As sensor device, a waveguide coupled micro-ring based approach is chosen which is manufactured in an 8” wafer level process. We will show that the co-integration with a reproducible, scalable and low-cost microfluidic interface is the main challenge which needs to be overcome for future application of silicon technology based PIC sensor chips

Workshops at IMS2023

Lists future events that should be of interest to practitioners and researchers.Peer ReviewedPostprint (published version

Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies

Working for the photolithography tool manufacturer leader sometimes gives me the impression of how complex and specific is the sector I am working on. This master thesis topic came with the goal of getting the overall picture of the state-of-the-art: stepping out and trying to get a helicopter view usually helps to understand where a process is in the productive chain, or what other firms and markets are doing to continue improvingUniversidad de sevilla.Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico

US Microelectronics Packaging Ecosystem: Challenges and Opportunities

The semiconductor industry is experiencing a significant shift from traditional methods of shrinking devices and reducing costs. Chip designers actively seek new technological solutions to enhance cost-effectiveness while incorporating more features into the silicon footprint. One promising approach is Heterogeneous Integration (HI), which involves advanced packaging techniques to integrate independently designed and manufactured components using the most suitable process technology. However, adopting HI introduces design and security challenges. To enable HI, research and development of advanced packaging is crucial. The existing research raises the possible security threats in the advanced packaging supply chain, as most of the Outsourced Semiconductor Assembly and Test (OSAT) facilities/vendors are offshore. To deal with the increasing demand for semiconductors and to ensure a secure semiconductor supply chain, there are sizable efforts from the United States (US) government to bring semiconductor fabrication facilities onshore. However, the US-based advanced packaging capabilities must also be ramped up to fully realize the vision of establishing a secure, efficient, resilient semiconductor supply chain. Our effort was motivated to identify the possible bottlenecks and weak links in the advanced packaging supply chain based in the US.Comment: 22 pages, 8 figure

National Center for Advanced Information Components Manufacturing. Program summary report, Volume II

The National Center for Advanced Information Components Manufacturing focused on manufacturing research and development for flat panel displays, advanced lithography, microelectronics, and optoelectronics. This report provides an overview of the program, program history, summaries of the technical projects, and key program accomplishments

A Review on Key Issues and Challenges in Devices Level MEMS Testing

The present review provides information relevant to issues and challenges in MEMS testing techniques that are implemented to analyze the microelectromechanical systems (MEMS) behavior for specific application and operating conditions. MEMS devices are more complex and extremely diverse due to the immersion of multidomains. Their failure modes are distinctive under different circumstances. Therefore, testing of these systems at device level as well as at mass production level, that is, parallel testing, is becoming very challenging as compared to the IC test, because MEMS respond to electrical, physical, chemical, and optical stimuli. Currently, test systems developed for MEMS devices have to be customized due to their nondeterministic behavior and complexity. The accurate measurement of test systems for MEMS is difficult to quantify in the production phase. The complexity of the device to be tested required maturity in the test technique which increases the cost of test development; this practice is directly imposed on the device cost. This factor causes a delay in time-to-market

A Review on Key Issues and Challenges in Devices Level MEMS Testing

The present review provides information relevant to issues and challenges in MEMS testing techniques that are implemented to analyze the microelectromechanical systems (MEMS) behavior for specific application and operating conditions. MEMS devices are more complex and extremely diverse due to the immersion of multidomains. Their failure modes are distinctive under different circumstances. Therefore, testing of these systems at device level as well as at mass production level, that is, parallel testing, is becoming very challenging as compared to the IC test, because MEMS respond to electrical, physical, chemical, and optical stimuli. Currently, test systems developed for MEMS devices have to be customized due to their nondeterministic behavior and complexity. The accurate measurement of test systems for MEMS is difficult to quantify in the production phase. The complexity of the device to be tested required maturity in the test technique which increases the cost of test development; this practice is directly imposed on the device cost. This factor causes a delay in time-to-market

Nanoelectromechanical Sensors based on Suspended 2D Materials

The unique properties and atomic thickness of two-dimensional (2D) materials enable smaller and better nanoelectromechanical sensors with novel functionalities. During the last decade, many studies have successfully shown the feasibility of using suspended membranes of 2D materials in pressure sensors, microphones, accelerometers, and mass and gas sensors. In this review, we explain the different sensing concepts and give an overview of the relevant material properties, fabrication routes, and device operation principles. Finally, we discuss sensor readout and integration methods and provide comparisons against the state of the art to show both the challenges and promises of 2D material-based nanoelectromechanical sensing.Comment: Review pape