New proposed method for traceability dissemination of capacitance measurements

Capacitance measurements at the National Institute of Standards (NIS), Egypt, are traceable to the Bureau International des Poids et Mesures (BIPM). It calibrates the main NIS standard capacitors, AH11A. In this paper, traceability of the BIPM capacitance measurements could be used to evaluate a new accurate measurement method through an Ultra-Precision Capacitance Bridge. The new method is carefully described by introducing some necessary equations and a demonstrating chart. Verification of this new method has been realized by comparing its results for the 10 pF and 100 pF capacitance standards with the results obtained by the conventional substitution method at 1 kHz and 1.592 kHz. The relative differences between the two methods are about 0.3 µF/F, which reflect the accuracy of the new measurement method. For higher capacitance ranges, the new measurement method has been applied for the capacitance measurements up to 1 μF at 1 kHz. The relative differences between the two methods are in the range of 5.5 µF/F on the average which proves the acceptable accuracy and the reliability of the new method to be used

Long-term effects of thermal variation on the performance of Balanced Twisted Pair Cabling

Remote powering over the Ethernet (including PoE, PoE+ and PoE++) is currently trending as a cost-effective option to power networked devices using balanced twisted pair cabling. As technology advances and Ethernet penetration grows, more devices are deployed, thereby increasing the cabling density to support these devices. Power delivery through Ethernet cables has numerous benefits, including cost and space saving. However, concurrent high-power transmission and installation conditions could induce local heating, and thus, thermal variation may occur in the cable bundles, and these can be exacerbated by the installation conditions, and sometimes by extreme weather conditions. Over a long time, all these could modify the cable properties, thus affecting the performance of the cabling system and thereby impacting the Ethernet signal integrity. Although Joule heating of the cable bundle is primarily assumed to be concomitants of current transmission through the cable, several fundamental questions around these processes are not yet fully answered. They include: Do cable heating and thermal variations influence the designed transmission parameters of the cable? If yes, how can the cause(s) and effects be accurately measured and reliably validated? In answering some of these questions, a series of experiments were developed and adopted to (1) assess cable bundle heating (2) assess the performance of Balanced Twisted Pair cables subject to repeated thermal variation, both within the specified operating range and beyond to account for the situations where high temperature and localised heating might stress the cables beyond the designed or expected levels (3) assess the performance of Ethernet cable dielectrics to understand some of the root causes of Ethernet cable performance degradation. The outcome of the research showed that high power (100 watts) deployment over bundled and insulated unshielded Ethernet cables triggered an extremely high-temperature increase (~ 1400C) that resulted in mechanical failure of the cables’ dielectrics and a short circuit between the copper conductors of the cables. Larger cable conductor size, screening of the twisted pair along with Fluoropolymers as the conductor insulation helped the shielded cables not to reach a point of failure when tested in the insulated environments and at high power levels even though there was a temperature rise on the cables. Moreover, repeated resistive and non- resistive heating have adverse effects on the electrical properties and transmission parameters of Balanced Twisted Pair cables, most notably in the first few cycles. The impact was more pronounced during the cooling phase than the heating phase. Also, the thermal impact was more accentuated in insulated operating condition than in ventilated operating condition. The electrical length of the cable measured by the tester decreased by 0.7 m 5 due to the effect of repeated non-resistive heating in an insulated environment and at a high temperature of ~1200C but decreased by 0.4 m with ~700C in a similar insulated environment. Phase drifts in Balanced Twisted Pair cables were observed to be dependent on the combined effects of mechanical dimension, dielectric constant and frequency. Thermal variation caused a phase change in the Return Loss (RL) signal from 630 to 900, from 900 to 1350 and from 1350 to 3150 respectively. The RL performance of Category 6 U/UTP CoMmunications Plenum rated (CMP) cable failed at 200C and recovered at 230C initially, but after the electrical length of the cable had decreased, subsequent failure and recovery temperatures accelerated towards higher temperature (400C). Similarly, the transition temperatures of the bandwidth of the cavity loaded with the Fluorinated Ethylene Propylene (FEP) from the Category 6 U/UTP CMP cable accelerated during the prolonged thermal cycling. The maximum reduction in the RL value of Category 6A F/UTP cable due to the 40 thermal cycles conducted was observed to be 5 % per degree, whereas the maximum Insertion Loss (IL) increase was 5.8 % per degree. Moreover, for the 24 thermal cycles conducted on Category 6 U/UTP CMP cable, an increase in IL of ~8.3 % per degree was observed while RL decreased by ~6.8 % per degree. Using the Features Selective Validation technique, the comparison between the baseline performance and long-term performance of Category 6A F/UTP permanent link (PL) showed a fair agreement, which implies degradation in the performance of the cable. Furthermore, results showed that impedance varied significantly along the length of the cable due to localised heating of the cable. The impedance along the unheated sides of the cable reverted at every 2 (0.4 m) and 4 (0.2 m) but the impedance profile of the heated middle portion of the cable varied significantly. The results of the Scanning Electron Microscope revealed the deformation in the conductor insulation of a twisted pair sample. Furthermore, the adhesion of the twisted pair conductor insulation to its copper conductor was also observed to be affected near the end of the twisted pair sample. Connector impedance mismatch was observed to be severe on the split pair pins (pair 3,6) than other pairs in the cable. The connector impedance mismatch also dominated the Near End Crosstalk (NEXT) loss at frequencies around 35 MHz. The repeated heating of the cable to a higher temperature of 1200C caused the loss of the PL at room temperature and a DC contact resistance issue which of course resulted in poor intra-pair resistance unbalance between the split pair. The Transverse Conversion Loss (TCL) and Equal Level Transverse Conversion Transfer Loss (ELTCTL) of Category 6 U/UTP CMP PL revealed some imbalances in the structure of the twisted pairs. Also, the equivalent differential mode noise voltages for the TCL values of the cable revealed a voltage spike following the decrease in the electrical length of the cable. More also, Crosstalk performance between the longest and shortest pair in the Category 6A 6 F/UTP cable was also observed to be better due to the heating of the cable in comparison to the crosstalk loss measured due to the cooling of the cable. Crosstalk performance of the portion insulated cables was initially worse during the first few heating and cooling cycles but improved afterwards. In addition, crosstalk, which was not initially present at the reference plane of the permanent link, was observed to increase rapidly from the point where the electrical length decreased. The increase in temperature to ~650C caused an accentuated frequency shift in the resonance of the FEP, which is the probable cause of the immediate performance degradation of the Category 6 U/UTP CMP cable. The dielectric constant of the extracted FEP rod sample from Category 6 U/UTP CMP cable increased as a consequence of prolonged thermal cycling, particularly during the cooling phase, which also suggests the root cause of the poor RL performance observed during the cooling phase. The increased loss tangent of the FEP during thermal cycling also indicates that IL performance degradation of the Ethernet cables will increase during the heating and cooling process in Ethernet cables. Also, on a long-term, IL performance will drift due to thermal cycling. Furthermore, various signal phase transitions were recorded during the heating and cooling of the cable and its dielectric due to the different behaviour of the molecular transitions. As a result, an echo of RL was measured during the transition between the intermittent and prolonged thermal cycling of the cable, of which can be correlated to the spurious resonance, observed in the resonance of the FEP sample during the transition period. Thus, it could be inferred that immediate and longterm effects of thermal variation influence the designed electrical properties and transmission parameters of Balanced Twisted Pair cables. Also, an immediate and long-term effect of thermal variation on the conductor insulation of the cable has a direct effect on the performance of Balanced Twisted Pair Cables

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Metrological characterisation of Low Power Voltage Transformers by using impulse response analysis

this thesis presents a new approach in dealing with characterize LPVT and proposes determining the impulse response of LPVT, purposing to find transfer function (h(t)) which contains most electrical characteristics of LPVTs as a dynamic system

Novel techniques for the design and practical realization of switched-capacitor circuits in deep-submicron CMOS technologies

Dissertação apresentada para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores pela Universidade Nova de Lisboa, Faculdade de Ciências e TecnologiaSwitches presenting high linearity are more and more required in switched-capacitor circuits,namely in 12 to 16 bits resolution analog-to-digital converters. The CMOS technology evolves continuously towards lower supply voltages and, simultaneously, new design techniques are necessary to fulfill the realization of switches exhibiting a high dynamic range and a distortion compatible with referred resolutions. Moreover, with the continuously downing of the sizes, the physic constraints of the technology must be considered to avoid the excessive stress of the devices when relatively high voltages are applied to the gates. New switch-linearization techniques, with high reliability, must be necessarily developed and demonstrated in CMOS integrated circuits. Also, the research of new structures of circuits with switched-capacitor is permanent. Simplified and efficient structures are mandatory, adequate to the new demands emerging from the proliferation of portable equipments, necessarily with low energy consumption while assuring high performance and multiple functions. The work reported in this Thesis comprises these two areas. The behavior of the switches under these new constraints is analyzed, being a new and original solution proposed, in order to maintain the performance. Also, proposals for the application of simpler clock and control schemes are presented, and for the use of open-loop structures and amplifiers with localfeedback. The results, obtained in laboratory or by simulation, assess the feasibility of the presented proposals