A High-Temperature, High-Voltage SOI Gate Driver Integrated Circuit with High Drive Current for Silicon Carbide Power Switches

High-temperature integrated circuit (IC) design is one of the new frontiers in microelectronics that can significantly improve the performance of the electrical systems in extreme environment applications, including automotive, aerospace, well-logging, geothermal, and nuclear. Power modules (DC-DC converters, inverters, etc.) are key components in these electrical systems. Power-to-volume and power-to-weight ratios of these modules can be significantly improved by employing silicon carbide (SiC) based power switches which are capable of operating at much higher temperature than silicon (Si) and gallium arsenide (GaAs) based conventional devices. For successful realization of such high-temperature power electronic circuits, associated control electronics also need to perform at high temperature. In any power converter, gate driver circuit performs as the interface between a low-power microcontroller and the semiconductor power switches. This dissertation presents design, implementation, and measurement results of a silicon-on-insulator (SOI) based high-temperature (\u3e200 _C) and high-voltage (\u3e30 V) universal gate driver integrated circuit with high drive current (\u3e3 A) for SiC power switches. This mixed signal IC has primarily been designed for automotive applications where the under-hood temperature can reach 200 _C. Prototype driver circuits have been designed and implemented in a Bipolar-CMOS- DMOS (BCD) on SOI process and have been successfully tested up to 200 _C ambient temperature driving SiC switches (MOSFET and JFET) without any heat sink and thermal management. This circuit can generate 30V peak-to-peak gate drive signal and can source and sink 3A peak drive current. Temperature compensating and temperature independent design techniques are employed to design the critical functional units like dead-time controller and level shifters in the driver circuit. Chip-level layout techniques are employed to enhance the reliability of the circuit at high temperature. High-temperature test boards have been developed to test the prototype ICs. An ultra low power on-chip temperature sensor circuit has also been designed and integrated into the gate-driver die to safeguard the driver circuit against excessive die temperature (_ 220 _C). This new temperature monitoring approach utilizes a reverse biased p-n junction diode as the temperature sensing element. Power consumption of this sensor circuit is less than 10 uW at 200 _C

Ultra-low Voltage Digital Circuits and Extreme Temperature Electronics Design

Certain applications require digital electronics to operate under extreme conditions e.g., large swings in ambient temperature, very low supply voltage, high radiation. Such applications include sensor networks, wearable electronics, unmanned aerial vehicles, spacecraft, and energyharvesting systems. This dissertation splits into two projects that study digital electronics supplied by ultra-low voltages and build an electronic system for extreme temperatures. The first project introduces techniques that improve circuit reliability at deep subthreshold voltages as well as determine the minimum required supply voltage. These techniques address digital electronic design at several levels: the physical process, gate design, and system architecture. This dissertation analyzes a silicon-on-insulator process, Schmitt-trigger gate design, and asynchronous logic at supply voltages lower than 100 millivolts. The second project describes construction of a sensor digital controller for the lunar environment. Parts of the digital controller are an asynchronous 8031 microprocessor that is compatible with synchronous logic, memory with error detection and correction, and a robust network interface. The digitial sensor ASIC is fabricated on a silicon-germanium process and built with cells optimized for extreme temperatures

Remote powered system for passive optical networks

Mestrado em Engenharia Electrónica e TelecomunicaçõesAs redes passivas são cada vez mais uma realidade. Os standards estão a desenvolver-se rapidamente (NG-PON, G-PON, etc), e cada vez mais o consumidor final tem maior necessidade de largura de banda, que, numa primeira fase, irá certamente, ser distribuída por redes passivas integralmente ópticas. As redes passivas são, por si, uma solução interessante para os operadores, pois, sendo passivas minimizam os custos de manutenção. No entanto, o reverso desta passividade e transparência, é que estas podem ser alteradas por simples aumento do número de ramais de uma forma independente e potencialmente incontrolada. Um aumento do tráfego, bem como um crescente de procura de novos serviços e larguras de banda, vêm forçar o desenvolvimento de novas tecnologias que permitam um redimensionamento e redefinição da rede, nomeadamente nós ópticos transparentes. O objectivo principal deste trabalho é estudar os processos de alimentação remota de sistemas de comutação e reconfiguração para utilização em redes ópticas passivas, e fazer uma implementação de alguns modelos para teste. De salientar que este projecto enquadra-se no projecto Europeu “SARDANA” e nas redes de excelência “BONE” e “Euro-FOS”. ABSTRACT: The passive networks are becoming a reality. The Standards are evolving rapidly (NG-PON, G-PON, etc), and now, the consumer, more than ever, has a major necessity for bandwidth, which, in a first stage, will certainly be distributed by fully passive optical networks. The passive networks are, on their own, an interesting solution for operators, because, being passive, minimize the maintenance costs. However, the other side of the passiveness and transparency is that it can be altered by simple increase of the number of branches in a independent way and potentially uncontrolled. An increase of traffic, as an increasing search of new services and bandwidth, are forcing the development of new technologies which will allow a network resizing and redefinition, in particular, the transparent optical nodes. The main objective of this work is study the remote powering processes for commutable and reconfigurable systems, to be used in passive optical networks, and implementing some models for testing. Note that this Project falls within the European project “SARDANA” and in the networks of excellence “BONE” and “Euro-FOS”

Modified Differential Cascode Voltage Switch Logic Optimized for Sub-threshold Voltage Operation

Ultra-low sub-threshold voltage research has become increasingly important with the recent shift in consumer electronics towards low power designs for mobile, wearable, and implantable technologies. These applications are able to trade-off speed for reduced power consumption and reduced minimum operating voltage. This thesis studies circuit design solutions that focus on achieving the lowest minimum operating voltages. These applications are likely to be ones where the supply voltage may come from energy harvesting sources that are only able to source ultra-low voltages. The logic circuit presented in this thesis is a modified implementation of differential cascade voltage switch logic (DCVSL). Differential logic has improved ultra-low voltage performance over static CMOS logic and the modification to DCVSL offers a logic structure that can implement multi-input AND/NAND and OR/NOR gates while maintaining a stack height of one. This logic circuit is referred in this thesis as MOD-DCVSL. The modification requires the use of capacitive boosting to allow for normal logic operation. The results of this thesis show that differential logic styles are able to perform at lower minimum operating voltages compared to static CMOS logic styles but at the cost of larger delay and power compared to static CMOS. On average the differential implementations could operate at a minimum supply voltage 5mV lower than CMOS for two input implementations and 10mV lower for three input implementations. The delay of differential implementations was approximately double for both two and three input implementations. The power of the differential implementations are approximately 20% higher than static CMOS for two input implementations but this gap is narrowed to approximately 10% for three input implementations, here the lower minimum operating voltages allowed for decreased power consumption. Due to the consistently lower delay, static CMOS had a lower power delay product than the differential logic. When comparing only the differential logic, MOD-DCVSL offered negligible difference for two input implementations but was able to improve delay by 7% and power by 11% in the three input implementations

A Process Variation Tolerant Self-Compensation Sense Amplifier Design

As we move under the aegis of the Moore\u27s law, we have to deal with its darker side with problems like leakage and short channel effects. Once we go beyond 45nm regime process variations also have emerged as a significant design concern.Embedded memories uses sense amplifier for fast sensing and typically, sense amplifiers uses pair of matched transistors in a positive feedback environment. A small difference in voltage level of applied input signals to these matched transistors is amplified and the resulting logic signals are latched. Intra die variation causes mismatch between the sense transistors that should ideally be identical structures. Yield loss due to device and process variations has never been so critical to cause failure in circuits. Due to growth in size of embedded SRAMs as well as usage of sense amplifier based signaling techniques, process variations in sense amplifiers leads to significant loss of yield for that we need to come up with process variation tolerant circuit styles and new devices. In this work impact of transistor mismatch due to process variations on sense amplifier is evaluated and this problem is stated. For the solution of the problem a novel self compensation scheme on sense amplifiers is presented on different technology nodes up to 32nm on conventional bulk MOSFET technology. Our results show that the self compensation technique in the conventional bulk MOSFET latch type sense amplifier not just gives improvement in the yield but also leads to improvement in performance for latch type sense amplifiers. Lithography related CD variations, fluctuations in dopant density, oxide thickness and parametric variations of devices are identified as a major challenge to the classical bulk type MOSFET. With the emerging nanoscale devices, SIA roadmap identifies FinFETs as a candidate for post-planar end-of-roadmap CMOS device. With current technology scaling issues and with conventional bulk type MOSFET on 32nm node our technique can easily be applied to Double Gate devices. In this work, we also develop the model of Double Gate MOSFET through 3D Device Simulator Damocles and TCAD simulator. We propose a FinFET based process variation tolerant sense amplifier design that exploits the back gate of FinFET devices for dynamic compensation against process variations. Results from statistical simulation show that the proposed dynamic compensation is highly effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node

Silicon Carbide Converters and MEMS Devices for High-temperature Power Electronics: A Critical Review

The significant advance of power electronics in today\u27s market is calling for high-performance power conversion systems and MEMS devices that can operate reliably in harsh environments, such as high working temperature. Silicon-carbide (SiC) power electronic devices are featured by the high junction temperature, low power losses, and excellent thermal stability, and thus are attractive to converters and MEMS devices applied in a high-temperature environment. This paper conducts an overview of high-temperature power electronics, with a focus on high-temperature converters and MEMS devices. The critical components, namely SiC power devices and modules, gate drives, and passive components, are introduced and comparatively analyzed regarding composition material, physical structure, and packaging technology. Then, the research and development directions of SiC-based high-temperature converters in the fields of motor drives, rectifier units, DC-DC converters are discussed, as well as MEMS devices. Finally, the existing technical challenges facing high-temperature power electronics are identified, including gate drives, current measurement, parameters matching between each component, and packaging technology

Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization