ENERGY-EFFICIENT AND SECURE HARDWARE FOR INTERNET OF THINGS (IoT) DEVICES

Internet of Things (IoT) is a network of devices that are connected through the Internet to exchange the data for intelligent applications. Though IoT devices provide several advantages to improve the quality of life, they also present challenges related to security. The security issues related to IoT devices include leakage of information through Differential Power Analysis (DPA) based side channel attacks, authentication, piracy, etc. DPA is a type of side-channel attack where the attacker monitors the power consumption of the device to guess the secret key stored in it. There are several countermeasures to overcome DPA attacks. However, most of the existing countermeasures consume high power which makes them not suitable to implement in power constraint devices. IoT devices are battery operated, hence it is important to investigate the methods to design energy-efficient and secure IoT devices not susceptible to DPA attacks. In this research, we have explored the usefulness of a novel computing platform called adiabatic logic, low-leakage FinFET devices and Magnetic Tunnel Junction (MTJ) Logic-in-Memory (LiM) architecture to design energy-efficient and DPA secure hardware. Further, we have also explored the usefulness of adiabatic logic in the design of energy-efficient and reliable Physically Unclonable Function (PUF) circuits to overcome the authentication and piracy issues in IoT devices. Adiabatic logic is a low-power circuit design technique to design energy-efficient hardware. Adiabatic logic has reduced dynamic switching energy loss due to the recycling of charge to the power clock. As the first contribution of this dissertation, we have proposed a novel DPA-resistant adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL). EE-SPFAL based circuits are energy-efficient compared to the conventional CMOS based design because of recycling the charge after every clock cycle. Further, EE-SPFAL based circuits consume uniform power irrespective of input data transition which makes them resilience against DPA attacks. Scaling of CMOS transistors have served the industry for more than 50 years in providing integrated circuits that are denser, and cheaper along with its high performance, and low power. However, scaling of the transistors leads to increase in leakage current. Increase in leakage current reduces the energy-efficiency of the computing circuits,and increases their vulnerability to DPA attack. Hence, it is important to investigate the crypto circuits in low leakage devices such as FinFET to make them energy-efficient and DPA resistant. In this dissertation, we have proposed a novel FinFET based Secure Adiabatic Logic (FinSAL) family. FinSAL based designs utilize the low-leakage FinFET device along with adiabatic logic principles to improve energy-efficiency along with its resistance against DPA attack. Recently, Magnetic Tunnel Junction (MTJ)/CMOS based Logic-in-Memory (LiM) circuits have been explored to design low-power non-volatile hardware. Some of the advantages of MTJ device include non-volatility, near-zero leakage power, high integration density and easy compatibility with CMOS devices. However, the differences in power consumption between the switching of MTJ devices increase the vulnerability of Differential Power Analysis (DPA) based side-channel attack. Further, the MTJ/CMOS hybrid logic circuits which require frequent switching of MTJs are not very energy-efficient due to the significant energy required to switch the MTJ devices. In the third contribution of this dissertation, we have investigated a novel approach of building cryptographic hardware in MTJ/CMOS circuits using Look-Up Table (LUT) based method where the data stored in MTJs are constant during the entire encryption/decryption operation. Currently, high supply voltage is required in both writing and sensing operations of hybrid MTJ/CMOS based LiM circuits which consumes a considerable amount of energy. In order to meet the power budget in low-power devices, it is important to investigate the novel design techniques to design ultra-low-power MTJ/CMOS circuits. In the fourth contribution of this dissertation, we have proposed a novel energy-efficient Secure MTJ/CMOS Logic (SMCL) family. The proposed SMCL logic family consumes uniform power irrespective of data transition in MTJ and more energy-efficient compared to the state-of-art MTJ/ CMOS designs by using charge sharing technique. The other important contribution of this dissertation is the design of reliable Physical Unclonable Function (PUF). Physically Unclonable Function (PUF) are circuits which are used to generate secret keys to avoid the piracy and device authentication problems. However, existing PUFs consume high power and they suffer from the problem of generating unreliable bits. This dissertation have addressed this issue in PUFs by designing a novel adiabatic logic based PUF. The time ramp voltages in adiabatic PUF is utilized to improve the reliability of the PUF along with its energy-efficiency. Reliability of the adiabatic logic based PUF proposed in this dissertation is tested through simulation based temperature variations and supply voltage variations

New Logic Synthesis As Nanotechnology Enabler (invited paper)

Nanoelectronics comprises a variety of devices whose electrical properties are more complex as compared to CMOS, thus enabling new computational paradigms. The potentially large space for innovation has to be explored in the search for technologies that can support large-scale and high- performance circuit design. Within this space, we analyze a set of emerging technologies characterized by a similar computational abstraction at the design level, i.e., a binary comparator or a majority voter. We demonstrate that new logic synthesis techniques, natively supporting this abstraction, are the technology enablers. We describe models and data-structures for logic design using emerging technologies and we show results of applying new synthesis algorithms and tools. We conclude that new logic synthesis methods are required to both evaluate emerging technologies and to achieve the best results in terms of area, power and performance

A statistical study of time dependent reliability degradation of nanoscale MOSFET devices

Charge trapping at the channel interface is a fundamental issue that adversely affects the reliability of metal-oxide semiconductor field effect transistor (MOSFET) devices. This effect represents a new source of statistical variability as these devices enter the nano-scale era. Recently, charge trapping has been identified as the dominant phenomenon leading to both random telegraph noise (RTN) and bias temperature instabilities (BTI). Thus, understanding the interplay between reliability and statistical variability in scaled transistors is essential to the implementation of a ‘reliability-aware’ complementary metal oxide semiconductor (CMOS) circuit design. In order to investigate statistical reliability issues, a methodology based on a simulation flow has been developed in this thesis that allows a comprehensive and multi-scale study of charge-trapping phenomena and their impact on transistor and circuit performance. The proposed methodology is accomplished by using the Gold Standard Simulations (GSS) technology computer-aided design (TCAD)-based design tool chain co-optimization (DTCO) tool chain. The 70 nm bulk IMEC MOSFET and the 22 nm Intel fin-shape field effect transistor (FinFET) have been selected as targeted devices. The simulation flow starts by calibrating the device TCAD simulation decks against experimental measurements. This initial phase allows the identification of the physical structure and the doping distributions in the vertical and lateral directions based on the modulation in the inversion layer’s depth as well as the modulation of short channel effects. The calibration is further refined by taking into account statistical variability to match the statistical distributions of the transistors’ figures of merit obtained by measurements. The TCAD simulation investigation of RTN and BTI phenomena is then carried out in the presence of several sources of statistical variability. The study extends further to circuit simulation level by extracting compact models from the statistical TCAD simulation results. These compact models are collected in libraries, which are then utilised to investigate the impact of the BTI phenomenon, and its interaction with statistical variability, in a six transistor-static random access memory (6T-SRAM) cell. At the circuit level figures of merit, such as the static noise margin (SNM), and their statistical distributions are evaluated. The focus of this thesis is to highlight the importance of accounting for the interaction between statistical variability and statistical reliability in the simulation of advanced CMOS devices and circuits, in order to maintain predictivity and obtain a quantitative agreement with a measured data. The main findings of this thesis can be summarised by the following points: Based on the analysis of the results, the dispersions of VT and ΔVT indicate that a change in device technology must be considered, from the planar MOSFET platform to a new device architecture such as FinFET or SOI. This result is due to the interplay between a single trap charge and statistical variability, which has a significant impact on device operation and intrinsic parameters as transistor dimensions shrink further. The ageing process of transistors can be captured by using the trapped charge density at the interface and observing the VT shift. Moreover, using statistical analysis one can highlight the extreme transistors and their probable effect on the circuit or system operation. The influence of the passgate (PG) transistor in a 6T-SRAM cell gives a different trend of the mean static noise margin

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Predicting power scalability in a reconfigurable platform

This thesis focuses on the evolution of digital hardware systems. A reconfigurable platform is proposed and analysed based on thin-body, fully-depleted silicon-on-insulator Schottky-barrier transistors with metal gates and silicide source/drain (TBFDSBSOI). These offer the potential for simplified processing that will allow them to reach ultimate nanoscale gate dimensions. Technology CAD was used to show that the threshold voltage in TBFDSBSOI devices will be controllable by gate potentials that scale down with the channel dimensions while remaining within appropriate gate reliability limits. SPICE simulations determined that the magnitude of the threshold shift predicted by TCAD software would be sufficient to control the logic configuration of a simple, regular array of these TBFDSBSOI transistors as well as to constrain its overall subthreshold power growth. Using these devices, a reconfigurable platform is proposed based on a regular 6-input, 6-output NOR LUT block in which the logic and configuration functions of the array are mapped onto separate gates of the double-gate device. A new analytic model of the relationship between power (P), area (A) and performance (T) has been developed based on a simple VLSI complexity metric of the form ATσ = constant. As σ defines the performance “return” gained as a result of an increase in area, it also represents a bound on the architectural options available in power-scalable digital systems. This analytic model was used to determine that simple computing functions mapped to the reconfigurable platform will exhibit continuous power-area-performance scaling behavior. A number of simple arithmetic circuits were mapped to the array and their delay and subthreshold leakage analysed over a representative range of supply and threshold voltages, thus determining a worse-case range for the device/circuit-level parameters of the model. Finally, an architectural simulation was built in VHDL-AMS. The frequency scaling described by σ, combined with the device/circuit-level parameters predicts the overall power and performance scaling of parallel architectures mapped to the array

Silicon Nanodevices

This book is a collection of scientific articles which brings research in Si nanodevices, device processing, and materials. The content is oriented to optoelectronics with a core in electronics and photonics. The issue of current technology developments in the nanodevices towards 3D integration and an emerging of the electronics and photonics as an ultimate goal in nanotechnology in the future is presented. The book contains a few review articles to update the knowledge in Si-based devices and followed by processing of advanced nano-scale transistors. Furthermore, material growth and manufacturing of several types of devices are presented. The subjects are carefully chosen to critically cover the scientific issues for scientists and doctoral students

Exploring valleytronics in 2D transition metal dichalcogenides

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.Cataloged from PDF version of thesis.Includes bibliographical references (pages 129-144).Monolayer transition metal dichalcogenides (TMDs) exhibit distinct electrical and optical properties according to the relative occupation of each of two valleys in their dispersion relation. The resulting valley degree of freedom is robust, linked to a large spin-orbit splitting between valence bands, and shows promise in electro-optical devices or as an information token for logic applications. In order to explore applications of these properties, monolayer crystals are required that have reduced intervalley scattering. To date, the majority of valley-related studies have focused on exfoliated samples for their quality and ease of production. In this thesis, valley polarization is explored in monolayer tungsten disulfide (WS₂) synthesized by chemical vapor transport (CVT). This novel method of bottom-up growth relies on halide-driven vapor transport commonly utilized in bulk crystal growth. Using a small amount of sodium chloride salt as a source of chlorine, non-volatile WS₂ can react to form gaseous tungsten chloride and sulfur. With an open tube system, a controlled reaction generates mono- and few- layer WS₂ crystals. These crystals have excellent optical properties and exhibit a degree of valley polarization near 50% at 77 K and up to 30% at room temperature. This surpasses previous values reported in WS₂ . By decoupling pump photon and thermal energy, valley depolarization shows the characteristics of an electron-hole exchange interaction rather than nonradiative scattering. These results offer the initial groundwork for future devices that use the coupled valley-spin degree of freedom as a robust token of information, promising reduced power consumption compared to conventional MOSFET-based electronics.by Brian Joseph Modtland.Ph. D

Formation of Si Nanocrystals for Single Electron Transistors by Ion Beam Mixing and Self-Organization – Modeling and Simulation

The replacement of the conventional field effect transistor (FET) by single electron transistors (SET) would lead to high energy savings and to devices with significantly longer battery life. There are many production approaches, but mostly for specimens in the laboratory. Most of them suffer from the fact that they either only work at cryogenic temperatures, have a low production yield or are not reproducible and each unit works in a unique way. A room temperature (RT) operating SET can be configured by inserting a small (few nm diameters) Si-Nanocrystal (NC) into a thin (<10 nm) SiO2 interlayer in Si. Industrial production has so far been excluded due to a lack of manufacturing processes. Classical technologies such as lithography fail to produce structures in this small scale. Even electron beam lithography or extreme ultraviolet lithography are far from being able to realize these structures in mass production. However, self-organization processes enable structures to be produced in any order of magnitude down to atomic sizes. Earlier studies realized similar systems using a layer of Si-NCs to fabricate a non-volatile memory by using the charge of the NCs for data storage. Based on this, it is very promising to use it for the realization of the SET. The self-organization depends only on the start configuration of the system and the boundary conditions during the process. These macroscopic conditions control the self-formed structures. In this work, ion beam irradiation is used to form the initial configuration, and thermal annealing is used to drive self-organization. A Si/SiO2/Si stack is irradiated and transforms the stack into Si/SiOx/Si by ion beam mixing (IBM) of the two Si/SiO2 interfaces. The oxide becomes metastable and the subsequent thermal treatment induces selforganization, which might leave a single Si-NC in the SiO2 layer for a sufficiently small mixing volume. The transformation of the planar SiOx layer (restriction only in one dimension) into a small SiOx volume (restriction in all three dimensions) is done by etching nanopillars with a diameter of less than 10nm. This forms a small SiOx plate embedded between two Si layers. The challenge is to control the self-organization process. In this work, simulation was used to investigate dependencies and parameter optimization. The ion mixing simulations were performed using binary collision approximation (BCA), followed by kinetic Monte Carlo (KMC) simulations of the decomposition process, which gave good qualitative agreement with the structures observed in related experiments. Quantitatively, however, the BCA simulation seemed to overestimate the mixing effect. This is due to the neglect of the positive entropy of the Si-SiO2 system mixing, i.e. the immiscibility counteracts the collisional mixing. The influence of this mechanism increases with increasing ion fluence. Compared to the combined BCA and KMC simulations, a larger ion mixing fluence has to be applied experimentally to obtain the predicted nanocluster morphology. To model the ion beam mixing of the Si/SiO2 interface, phase field methods have been applied to describe the influence of chemical effects during the irradiation of buried SiO2 layers by 60 keV Si+ ions at RT and thermal annealing at 1050°C. The ballistic collisional mixing was modeled by an approach using Fick’s diffusion equation, and the chemical effects and the annealing were described by the Cahn Hilliard equation. By that, it is now possible to predict composition profiles of Si/SiO2 interfaces during irradiation. The results are in good agreement with the experiment and are used for the predictions of the NCs formation in the nanopillar. For the thermal treatment model extensions were also necessary. The KMC simulations of Si-SiO2 systems in the past were based on normed time and temperature, so that the diffusion velocity of the components was not considered. However, the diffusion of Si in SiO2 and SiO2 in Si differs by several orders of magnitude. This cannot be neglected in the thermal treatment of the Si/SiO2 interface, because the processes that differ in speed in this order of magnitude are only a few nanometers apart. The KMC method was extended to include the different diffusion coefficients of the Si-SiO2 system. This allows to extensively investigate the influence of the diffusion. The phase diagram over temperature and composition was examined regarding decomposition (nucleation as well as spinodal decomposition) and growing of NCs. Using the methods and the knowledge gained about the system, basic simulations for the individual NC formation in the nanopillar were carried out. The influence of temperature, diameter, and radiation fluence was discussed in detail on the basis of simulation results