Анализ влияния расширенной конфигурации n-МОП транзистора на параметры 4x1 мультиплексора

Полный текст доступен на сайте издания по подписке: http://radio.kpi.ua/article/view/S0021347018030044В статье приведен анализ потребляемой мощности и величины задержки 4x1 мультиплексора на базе расширенной конфигурации n-МОП транзистора AT-NMOS (Augmented Transistor NMOS). Рассмотрено влияние различных уровней общей ширины канала транзистора на характеристики мощности утечки и задержки в случае 45 нм технологии. Установлено, что параметр эффективности улучшается в предлагаемой конструкции на основе расширенной конфигурации p-МОП транзистора с закороченным участком затвор–исток и n-МОП структурой ASG-S PMOS-NMOS (Augmented Shorted Gate-Source PMOS with NMOS) по сравнению с 4x1 мультиплексором на основе конфигурации расширенного n-МОП транзистора со статическим порогом ST-ATNMOS (Static Threshold AT-NMOS). При этой комбинации получены желаемые параметры рабочей характеристики проектируемой схемы. В работе рассмотрено два типа моделей для 4x1 мультиплексора. Показано, что мощность утечки существенно сокращается. Характеристика задержки также улучшается до 5% при источнике питания 1 В в случае рассмотрения многоуровневой ширины канала транзистора для оценки моделей 4x1 мультиплексора на основе различных конфигураций расширенного n-МОП транзистора AT-NMOS. Моделирование осуществлялось при использовании моделирующих программ Cadence Analog Virtuoso и Spectre Simulator применительно к 45 нм КМОП-технологии

Low Power Digital Filter Implementation in FPGA

Digital filters suitable for hearing aid application on low power perspective have been developed and implemented in FPGA in this dissertation. Hearing aids are primarily meant for improving hearing and speech comprehensions. Digital hearing aids score over their analog counterparts. This happens as digital hearing aids provide flexible gain besides facilitating feedback reduction and noise elimination. Recent advances in DSP and Microelectronics have led to the development of superior digital hearing aids. Many researchers have investigated several algorithms suitable for hearing aid application that demands low noise, feedback cancellation, echo cancellation, etc., however the toughest challenge is the implementation. Furthermore, the additional constraints are power and area. The device must consume as minimum power as possible to support extended battery life and should be as small as possible for increased portability. In this thesis we have made an attempt to investigate possible digital filter algorithms those are hardware configurable on low power view point. Suitability of decimation filter for hearing aid application is investigated. In this dissertation decimation filter is implemented using ‘Distributed Arithmetic’ approach.While designing this filter, it is observed that, comb-half band FIR-FIR filter design uses less hardware compared to the comb-FIR-FIR filter design. The power consumption is also less in case of comb-half band FIR-FIR filter design compared to the comb-FIR-FIR filter. This filter is implemented in Virtex-II pro board from Xilinx and the resource estimator from the system generator is used to estimate the resources. However ‘Distributed Arithmetic’ is highly serial in nature and its latency is high; power consumption found is not very low in this type of filter implementation. So we have proceeded for ‘Adaptive Hearing Aid’ using Booth-Wallace tree multiplier. This algorithm is also implemented in FPGA and power calculation of the whole system is done using Xilinx Xpower analyser. It is observed that power consumed by the hearing aid with Booth-Wallace tree multiplier is less than the hearing aid using Booth multiplier (about 25%). So we can conclude that the hearing aid using Booth-Wallace tree multiplier consumes less power comparatively. The above two approached are purely algorithmic approach. Next we proceed to combine circuit level VLSI design and with algorithmic approach for further possible reduction in power. A MAC based FDF-FIR filter (algorithm) that uses dual edge triggered latch (DET) (circuit) is used for hearing aid device. It is observed that DET based MAC FIR filter consumes less power than the traditional (single edge triggered, SET) one (about 41%). The proposed low power latch provides a power saving upto 65% in the FIR filter. This technique consumes less power compared to previous approaches that uses low power technique only at algorithmic abstraction level. The DET based MAC FIR filter is tested for real-time validation and it is observed that it works perfectly for various signals (speech, music, voice with music). The gain of the filter is tested and is found to be 27 dB (maximum) that matches with most of the hearing aid (manufacturer’s) specifications. Hence it can be concluded that FDF FIR digital filter in conjunction with low power latch is a strong candidate for hearing aid application

Variability-Aware Design of Subthreshold Devices

Over the last 10 years, digital subthreshold logic circuits have been developed for applications in the ultra-low power design domain, where performance is not the priority. Recently, devices optimized for subthreshold operation have been introduced as potential construction blocks. However, for these devices, a strong sensitivity to process variations is expected due to the exponential relationship of the subthreshold drive current and the threshold voltage. In this thesis, a yield optimization technique is proposed to suppress the variability of a device optimized for subthreshold operation. The goal of this technique is to construct and inscribe a maximum yield cube in the 3-D feasible region composed of oxide thickness, gate length, and channel doping concentration. The center of this cube is chosen as the maximum yield design point with the highest immunity against variations. By using the technique, a transistor is optimized for subthreshold operation in terms of the desired total leakage current and intrinsic delay bounds. To develop the concept of the technique, sample devices are designed for 90nm and 65nm technologies. Monte Carlo simulations verify the accuracy of the technique for meeting power and delay constraints under technology-specific variances of the design parameters of the device

Weak Inversion Performance of CMOS and DCVSPG Logic Families in Sub-300mV Range

In this paper the advantages of using Differential Cascode Voltage Switch Pass Gate (DCVSPG) logic with regard to standard CMOS for subthreshold operation are presented. The two families are compared in terms of their performance and Energy-Delay-Product (EDP) figures. Multiple gates were simulated using 0.18µm standard CMOS technology. Simulation results show that DCVSPG NAND2 gate has 71%, DCVSPG NOR2 gate has 82% and DCVSPG full adder has 66% EDP savings over the CMOS counterparts

Pico-Watt Source-Coupled Logic Circuits

This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on different digital building blocks are provided to validate the main concepts presented in this paper. Implemented in conventional 0.18um CMOS technology, the bias current of each STSCL gate can be reduced below 10pA, which corresponds to a power-delay product (PDP) of less than 500aJ

A study on wireless hearing aids system configuration and simulation

Master'sMASTER OF SCIENC

A sub-threshold cell library and methodology

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 97-102).Sub-threshold operation is a compelling approach for energy-constrained applications where speed is of secondary concern, but increased sensitivity to process variation must be mitigated in this regime. With scaling of process technologies, random within-die variation has recently introduced another degree of complexity in circuit design. This thesis proposes approaches to mitigate process variation in sub-threshold circuits through device sizing, topology selection and fault-tolerant architecture. This thesis makes several contributions to a sub-threshold circuit design methodology. A formal analysis of device sizing trade-offs between delay, energy, and variability reveals that while minimum size devices provide lowest energy and delay in sub-threshold, their increased sensitivity to random dopant fluctuation may cause functional errors. A proposed variation-driven design approach enables consistent sizing of logic gates and registers for constant functional yield. A yield constraint imposes energy overhead at low power supply voltages and changes the minimum energy operating point of a circuit.(cont.) The optimal supply and device sizing depend on the topology of the circuit and its energy versus VDD characteristic. The analysis resulted in a 56-cell library in 65nm CMOS, which is incorporated in a computer-aided design flow. A test chip synthesized from this library implements a fault-tolerant FIR filter. Algorithmic error detection enables correction of transient timing errors due to delay variability in sub-threshold, and also allows the system frequency to be set more aggressively for the average case instead of the worst case.by Joyce Y.S. Kwong.S.M

Análise estatística dos momentos de primeira e segunda ordens dos algoritmos DLMS e LMS de erro filtrado modificados

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Engenharia Elétrica.Neste trabalho, são propostos modelos analíticos para os algoritmos delayed least-mean-square (DLMS) e least-mean-square (LMS) de erro filtrado modificados. Para cada um desses algoritmos, são obtidas as expressões que descrevem o comportamento dos momentos de primeira e segunda ordens e da curva de aprendizagem. Os modelos são obtidos sem invocar a suposição clássica da Teoria da Independência (TI), levando-se em conta a hipótese de adaptação lenta e considerando-se sinais de entrada Gaussianos. Os modelos aqui propostos não dependem do tipo de sinal de referência, podendo ser utilizados tanto para sinais de entrada brancos quanto para sinais coloridos. Para fins de comparação em cada caso, são também derivados modelos considerando-se a TI. A partir dos resultados obtidos, observa-se que os modelos propostos descrevem adequadamente o comportamento dos algoritmos em questão; em contraste, os modelos que consideram a TI não predizem tais algoritmos satisfatoriamente