An efficient hardware architecture for a neural network activation function generator

This paper proposes an efficient hardware architecture for a function generator suitable for an artificial neural network (ANN). A spline-based approximation function is designed that provides a good trade-off between accuracy and silicon area, whilst also being inherently scalable and adaptable for numerous activation functions. This has been achieved by using a minimax polynomial and through optimal placement of the approximating polynomials based on the results of a genetic algorithm. The approximation error of the proposed method compares favourably to all related research in this field. Efficient hardware multiplication circuitry is used in the implementation, which reduces the area overhead and increases the throughput

Modeling and Optimization of Chemical Mechanical Planarization (Cmp) Using Neural Networks, Anfis and Evolutionary Algorithms

Higher density nano-devices and more metallization layers in microelectronic chips are unceasing goals to the present semiconductor industry. However, topological imperfections (higher non-uniformity) on the wafer surfaces and lower material removal rates (MRR) seriously hamper these pursuing motivations. Since'90, industry has been using chemical mechanical planarization/polishing (CMP) to overcome these obstacles for fabricating integrated circuits (IC) with interconnect geometries of < 0.18 &amp;#956;m. Obviously, the much needed understanding of this new technique is derived basically on the ancient lapping process. Modeling and simulation are critical to transfer CMP from an engineering 'art' to an engineering 'science'. Many efforts in CMP modeling have been made in the last decade, but the available analytical MRR and surface uniformity models cannot precisely describe this highly complicated process, involving simultaneous chemical reactions (and etching), and mechanical abrasion. In this investigation, neural networks (NN), adaptive-based-network fuzzy inference system (ANFIS), and evolutionary algorithms (EA) techniques were applied to successfully overcome the aforementioned modeling and simulation problems. In addition, fine-tuning techniques for re-modifying ANFIS models for sparse-data case using are developed. Furthermore, multi-objective evolutionary algorithms (MOEA) are firstly applied to search for the optimal input settings for CMP process to trade-off the higher MRR and lower non-Uniformity by using the previously constructed models. The results also show the simulation of MOEA optimization can certainly provide accurate guidance to search the optimal input settings for CMP process to produce lower non-uniform wafer surfaces under higher MRR.Mechanical & Aerospace Engineerin

Multimodal transistors as ReLU activation functions in physical neural network classifiers

Artificial neural networks (ANNs) providing sophisticated, power-efficient classification are finding their way into thin-film electronics. Thin-film technologies require robust, layout-efficient devices with facile manufacturability. Here, we show how the multimodal transistor’s (MMT’s) transfer characteristic, with linear dependence in saturation, replicates the rectified linear unit (ReLU) activation function of convolutional ANNs (CNNs). Using MATLAB, we evaluate CNN performance using systematically distorted ReLU functions, then substitute measured and simulated MMT transfer characteristics as proxies for ReLU. High classification accuracy is maintained, despite large variations in geometrical and electrical parameters, as CNNs use the same activation functions for training and classification

Analogue neuromorphic systems.

This thesis addresses a new area of science and technology, that of neuromorphic systems, namely the problems and prospects of analogue neuromorphic systems. The subject is subdivided into three chapters. Chapter 1 is an introduction. It formulates the oncoming problem of the creation of highly computationally costly systems of nonlinear information processing (such as artificial neural networks and artificial intelligence systems). It shows that an analogue technology could make a vital contribution to the creation such systems. The basic principles of creation of analogue neuromorphic systems are formulated. The importance will be emphasised of the principle of orthogonality for future highly efficient complex information processing systems. Chapter 2 reviews the basics of neural and neuromorphic systems and informs on the present situation in this field of research, including both experimental and theoretical knowledge gained up-to-date. The chapter provides the necessary background for correct interpretation of the results reported in Chapter 3 and for a realistic decision on the direction for future work. Chapter 3 describes my own experimental and computational results within the framework of the subject, obtained at De Montfort University. These include: the building of (i) Analogue Polynomial Approximator/lnterpolatoriExtrapolator, (ii) Synthesiser of orthogonal functions, (iii) analogue real-time video filter (performing the homomorphic filtration), (iv) Adaptive polynomial compensator of geometrical distortions of CRT- monitors, (v) analogue parallel-learning neural network (backpropagation algorithm). Thus, this thesis makes a dual contribution to the chosen field: it summarises the present knowledge on the possibility of utilising analogue technology in up-to-date and future computational systems, and it reports new results within the framework of the subject. The main conclusion is that due to its promising power characteristics, small sizes and high tolerance to degradation, the analogue neuromorphic systems will playa more and more important role in future computational systems (in particular in systems of artificial intelligence)

Circuit paradigm in the 21

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An instruction systolic array architecture for multiple neural network types

Modern electronic systems, especially sensor and imaging systems, are beginning to incorporate their own neural network subsystems. In order for these neural systems to learn in real-time they must be implemented using VLSI technology, with as much of the learning processes incorporated on-chip as is possible. The majority of current VLSI implementations literally implement a series of neural processing cells, which can be connected together in an arbitrary fashion. Many do not perform the entire neural learning process on-chip, instead relying on other external systems to carry out part of the computation requirements of the algorithm. The work presented here utilises two dimensional instruction systolic arrays in an attempt to define a general neural architecture which is closer to the biological basis of neural networks - it is the synapses themselves, rather than the neurons, that have dedicated processing units. A unified architecture is described which can be programmed at the microcode level in order to facilitate the processing of multiple neural network types. An essential part of neural network processing is the neuron activation function, which can range from a sequential algorithm to a discrete mathematical expression. The architecture presented can easily carry out the sequential functions, and introduces a fast method of mathematical approximation for the more complex functions. This can be evaluated on-chip, thus implementing the entire neural process within a single system. VHDL circuit descriptions for the chip have been generated, and the systolic processing algorithms and associated microcode instruction set for three different neural paradigms have been designed. A software simulator of the architecture has been written, giving results for several common applications in the field

A Domain Adaptation approach for sequence modeling through Deep Learning in semiconductor manufacturing: adversarial training setup with Temporal Convolutional Network and Long-Short Term Memory models

Lo scopo di questo lavoro è sviluppare delle strategie di Deep Learning per estendere la ricerca precedente (gentner2021dbam,gentner2020enhancing) riguardante una mansione relativa all'ambito di Virtual Metrology in una produzione di semiconduttori. Questo vuole essere un confronto tra il modello sviluppato in precedenza e alcuni modelli più adatti ai dati di serie temporali in esame. La strategia utilizzata in questo problema si basa sul Domain Adaptation attraverso un'impostazione di Adversarial Training, un approccio recente che permette una miglior gestione in assenza di grandi quantità di dati e rende i modelli precedentemente addestrati riutilizzabili in scenari simili. Questa ricerca è incoraggiata per gli effetti che può portare in questo campo. Migliorare ulteriormente le prestazioni dei modelli utilizzati significa risparmiare sui costi di produzione, poiché permetterebbe di limitare ulteriormente test di conformità che portano al danneggiamento dei prodotti. Ciò comporta anche un possibile risparmio di materiali, aspetto importante dal punto di vista ecologico. Infine, è sempre più necessario considerare l'uso di modelli che utilizzano meno dati o sono più adatti a processi simili, come nel caso delle tecniche di Domain Adaptation. Questo è importante perché, come nell'applicazione considerata, i dati sono costosi da ottenere.The aim of this work is to develop Deep Learning strategies to extend previous research (gentner2021dbam,gentner2020enhancing) concerning a task related to Virtual Metrology field in a semiconductor manufacturing. This intends to compare the previously developed model and other models more suited to the time series data under examination. The strategy used in this problem is based on Domain Adaptation through an adversarial training setup; the approach is recent and promising, allowing for better management in the absence of large amounts of data and making previously trained models reusable in similar scenarios. This research is encouraged for its effects in this field; further improving the performance of the models used means savings on production costs, since it would limit conformity tests which lead to product damage. This also leads to a possible saving of materials, an important aspect from an ecological point of view. Finally, it is increasingly necessary to consider models that use less data or are more suitable for similar processes, as in the case of Domain Adaptation techniques. The latter aspect is relevant because the data is expensive to obtain in the considered application

Mesoporous Silica-Based Materials for Electronics-Oriented Applications

International audienceElectronics, and nanoelectronics in particular, represent one of the most promising branches of technology. The search for novel and more efficient materials seems to be natural here. Thus far, silicon-based devices have been monopolizing this domain. Indeed, it is justified since it allows for significant miniaturization of electronic elements by their densification in integrated circuits. Nevertheless, silicon has some restrictions. Since this material is applied in the bulk form, the miniaturization limit seems to be already reached. Moreover, smaller silicon-based elements (mainly processors) need much more energy and generate significantly more heat than their larger counterparts. In our opinion, the future belongs to nanostructured materials where a proper structure is obtained by means of bottom-up nanotechnology. A great example of a material utilizing nanostructuring is mesoporous silica, which, due to its outstanding properties, can find numerous applications in electronic devices. This focused review is devoted to the application of porous silica-based materials in electronics. We guide the reader through the development and most crucial findings of porous silica from its first synthesis in 1992 to the present. The article describes constant struggle of researchers to find better solutions to supercapacitors, lower the k value or redox-active hybrids while maintaining robust mechanical properties. Finally, the last section refers to ultra-modern applications of silica such as molecular artificial neural networks or super-dense magnetic memory storage

A neural computation to study the scaling capability of the undoped DG MOSFET

The DG MOSFET is one of the most promising candidates for further CMOS scaling beyond the year of 2010. It will be scaled down to various degrees upon a wide range of system/circuit requirements (such as high-performance, low standby power and low operating power). The key electrical parameter of the DG MOSFET is the subthreshold swing (S). In this paper, we present the applicability of the artificial neural network for the study of the scaling capability of the undoped DG MOSFET. The latter is based on the development of a semi-analytical model of the subthreshold swing (S) using the Finite Elements Method (FEM). Our results are discussed in order to draw some useful information about the ULSI technology