Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs

One of the major roadblocks in the continued scaling of standard CMOS technology is its alarmingly high leakage power consumption. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall energy efficiency of a system is still rooted in the MOSFET operating principle: an injection of thermally distributed carriers, which does not allow subthreshold swing (SS) lower than 60mV/dec at room temperature. Recently, a new class of steep-slope devices like Tunnel FETs (TFETs) and Negative-Capacitance FETs (NCFETs) have garnered intense interest due to their ability to surpass the 60mV/dec limit on SS at room temperature. The focus of this research is on the simulation and design of TFETs and NCFETs for ultra-low power logic and memory applications. Using full band quantum mechanical model within the Non-Equilibrium Greens Function (NEGF) formalism, source-underlapping has been proposed as an effective technique to lower the SS in GaSb-InAs TFETs. Band-tail states, associated with heavy source doping, are shown to significantly degrade the SS in TFETs from their ideal value. To solve this problem, undoped source GaSb-InAs TFET in an i-i-n configuration is proposed. A detailed circuit-to-system level evaluation is performed to investigate the circuit level metrics of the proposed devices. To demonstrate their potential in a memory application, a 4T gain cell (GC) is proposed, which utilizes the low-leakage and enhanced drain capacitance of TFETs to realize a robust and long retention time GC embedded-DRAMs. The device/circuit/system level evaluation of proposed TFETs demonstrates their potential for low power digital applications. The second part of the thesis focuses on the design space exploration of hysteresis-free Negative Capacitance FETs (NCFETs). A cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully-depleted SOI-FETs, and sub-10nm FinFETs shows that FDSOI and FinFET configurations greatly benefit the NCFET performance due to their undoped body and improved gate-control which enables better capacitance matching with the ferroelectric. A low voltage NC-FinFET operating down to 0.25V is predicted using ultra-thin 3nm FE-HZO. Next, we propose one-transistor ferroelectric NOR type (Fe-NOR) non-volatile memory based on HfZrOx ferroelectric FETs (FeFETs). The enhanced drain-channel coupling in ultrashort channel FeFETs is utilized to dynamically modulate memory window of storage cells thereby resulting in simple erase-, program-and read-operations. The simulation analysis predicts sub-1V program/erase voltages in the proposed Fe-NOR memory array and therefore presents a significantly lower power alternative to conventional FeRAM and NOR flash memories

High Quality Gate Dielectric/MoS2 Interfaces Probed by the Conductance Method

Two-dimensional materials provide a versatile platform for various electronic and optoelectronic devices, due to their uniform thickness and pristine surfaces. We probe the superior quality of 2D/2D and 2D/3D interfaces by fabricating molybdenum disulfide (MoS2)-based field effect transistors having hexagonal boron nitride (h-BN) and Al2O3 as the top gate dielectrics. An extremely low trap density of ~7x10^10 states/cm2-eV is extracted at the 2D/2D interfaces with h-BN as the top gate dielectric on the MoS2 channel. 2D/3D interfaces with Al2O3 as the top gate dielectric and SiOx as the nucleation layer exhibit trap densities between 7x10^10 and 10^11 states/cm2-eV, which is lower than previously reported 2D-channel/high-k-dielectric interface trap densities. The comparable values of trap time constants for both interfaces imply that similar types of defects contribute to the interface traps. This work establishes the case for van der Waals systems where the superior quality of 2D/2D and 2D/high-k dielectric interfaces can produce high performance electronic and optoelectronic devices

Silicon on ferroelectric insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Title from PDF of title page, viewed on March 12, 2014Thesis advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 116-131)Thesis (M. S.)--School of Computer and Engineering. University of Missouri--Kansas City, 2013Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in subnanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor’s Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-lowpower applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.Abstract -- List of illustrations - List of tables -- Acknowledgements -- Dedication -- Introduction -- Carbon nanotube field effect transistor -- Multi-gate transistors -FinFET -- Subthreshold swing -- Tunneling field effect transistors -- I-mos and nanowire fets -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for soi-finfet -- Silicon-on-ferroelectric insulator field effect transistor (SOF-FET) -- Current-voltage characteristics of sof-fet -- Advantages, manufacturing process and future work of the proposed device -- Appendix -- Reference

Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits

In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track and-hold (T/H) and comparator circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the comparator circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage

Simulation and Modeling of Novel Electronic Device Architectures with NESS (Nano-Electronic Simulation Software): A Modular Nano TCAD Simulation Framework

The modeling of nano-electronic devices is a cost-effective approach for optimizing the semiconductor device performance and for guiding the fabrication technology. In this paper, we present the capabilities of the new flexible multi-scale nano TCAD simulation software called NanoElectronic Simulation Software (NESS). NESS is designed to study the charge transport in contemporary and novel ultra-scaled semiconductor devices. In order to simulate the charge transport in such ultra-scaled devices with complex architectures and design, we have developed numerous simulation modules based on various simulation approaches. Currently, NESS contains a driftdiffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) modules. All modules are numerical solvers which are implemented in the C++ programming language, and all of them are linked and solved self-consistently with the Poisson equation. Here, we have deployed some of those modules to showcase the capabilities of NESS to simulate advanced nano-scale semiconductor devices. The devices simulated in this paper are chosen to represent the current state-of-the-art and future technologies where quantum mechanical effects play an important role. Our examples include ultra-scaled nanowire transistors, tunnel transistors, resonant tunneling diodes, and negative capacitance transistors. Our results show that NESS is a robust, fast, and reliable simulation platform which can accurately predict and describe the underlying physics in novel ultra-scaled electronic devices.European Union Horizon 2020 - 688101 SUPERAID7EPSRC UKRI Innovation Fellowship - EP/S001131/1 (QSEE), No. EP/P009972/1 (QUANTDEVMOD)H2020-FETOPEN-2019 s- No.862539-Electromed-FET OPEN.No. EP/S000259/1(Variability PDK for design based research on FPGA/neuro computing

Modeling Of Two Dimensional Graphene And Non-graphene Material Based Tunnel Field Effect Transistors For Integrated Circuit Design

The Moore’s law of scaling of metal oxide semiconductor field effect transistor (MOSFET) had been a driving force toward the unprecedented advancement in development of integrated circuit over the last five decades. As the technology scales down to 7 nm node and below following the Moore’s law, conventional MOSFETs are becoming more vulnerable to extremely high off-state leakage current exhibiting a tremendous amount of standby power dissipation. Moreover, the fundamental physical limit of MOSFET of 60 mV/decade subthreshold slope exacerbates the situation further requiring current transport mechanism other than drift and diffusion for the operation of transistors. One way to limit such unrestrained amount of power dissipation is to explore novel materials with superior thermal and electrical properties compared to traditional bulk materials. On the other hand, energy efficient steep subthreshold slope devices are the other possible alternatives to conventional MOSFET based on emerging novel materials. This dissertation addresses the potential of both advanced materials and devices for development of next generation energy efficient integrated circuits. Among the different steep subthreshold slope devices, tunnel field effect transistor (TFET) has been considered as a promising candidate after MOSFET. A superior gate control on source-channel band-to-band tunneling providing subthreshold slopes well below than 60 mV/decade. With the emergence of atomically thin two-dimensional (2D) materials, interest in the design of TFET based on such novel 2D materials has also grown significantly. Graphene being the first and the most studied among 2D materials with exotic electronic and thermal properties. This dissertation primarily considers current transport modeling of graphene based tunnel devices from transport phenomena to energy efficient integrated circuit design. Three current transport models: semi-classical, semi-quantum and numerical simulations are described for the modeling of graphene nanoribbon tunnel field effect transistor (GNR TFET) where the semi-classical model is in close agreement with the quantum transport simulation. Moreover, the models produced are also extended for integrated circuit design using Verilog-A hardware description language for logic design. In order to overcome the challenges associated with the band gap engineering for making graphene transistor for logic operation, the promise of graphene based interlayer tunneling transistors are discussed along with their existing fundamental physical limitation of subthreshold slope. It has been found that such interlayer tunnel transistor has very poor electrostatic gate control on drain current. It gives subthreshold slope greater than the thermionic limit of 60 mV/decade at room temperature. In order to resolve such limitation of interlayer tunneling transistors, a new type of transistor named “junctionless tunnel effect transistor (JTET)” has been invented and modeled for the first time considering graphene-boron nitride (BN)-graphene and molybdenum disulfide (MoS2)-boron nitride (BN) heterostructures, where the interlayer tunneling mechanism controls the source-drain ballistic transport instead of depleting carriers in the channel. Steep subthreshold slope, low power and high frequency THz operation are few of the promising features studied for such graphene and MoS2 JTETs. From current transport modeling to energy efficient integrated circuit design using Verilog-A has been carried out for these new devices as well. Thus, findings in this dissertation would suggest the exciting opportunity of a new class of next generation energy efficient material based transistors as switches

High-Performance Silicon Nanowire Electronics

This thesis explores 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications via the fabrication and testing of SiNW-based ring oscillators. Both SiNW surface treatments and dielectric annealing are reported for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio (~108), low drain-induced barrier lowering (~30 mV), high carrier mobilities (~269 cm2/V•s), and low subthreshold swing (~80 mV/dec). The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs is explored as well. The inverter demonstrates the highest voltage gain (~148) reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications. A set of novel charge-trap non-volatile memory devices based on high-performance SiNW FETs are well investigated. These memory devices integrate Fe2O3 quantum dots (FeO QDs) as charge storage elements. A template-assisted assembly technique is used to align FeO QDs into a close-packed, ordered matrix within the trenches that separate highly aligned SiNWs, and thus store injected charges. A Fowler-Nordheim tunneling mechanism describes both the program and erase operations. The memory prototype demonstrates promising characteristics in terms of large threshold voltage shift (~1.3 V) and long data retention time (~3 × 106 s), and also allows for key components to be systematically varied. For example, varying the size of the QDs indicates that larger diameter QDs exhibit a larger memory window, suggesting the QD charging energy plays an important role in the carrier transport. The device temperature characteristics reveal an optimal window for device performance between 275K and 350K. The flexibility of integrating the charge-trap memory devices with the SiNW logic devices offers a low-cost embedded non-volatile memory solution. A building block for a SiNW-based field-programmable gate array (FPGA) is proposed in the future work.</p