A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5° and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB

A 6-to-18 GHz tunable concurrent dual-band receiver front end for scalable phased arrays in 130nm CMOS

This paper presents a study and design of tunable concurrent dual-band receiver. Different system architectures and building blocks have been compared and analyzed. A tunable concurrent dual-band receiver front end has then been fabricated and characterized. It operates across a tri-tave 6-18 GHz bandwidth with a nominal 17-25 dB conversion gain, worst-case -15 dBm IIP3, and worst-case -24.5 dBm ICP 1 dB

A Multiband, Low Power and Low Phase Noise CMOS Voltage-Controlled Oscillator with NMOS Varactor for UWB Applications

A multiband low power and low phase noise LC-tank Voltage Controlled Oscillator (VCO) is designed for low band channels of the standard IEEE 802.15.4a. The LC-VCO uses the structure of complementary cross-coupled differential negative resistance and tank circuit, which contains varactor arrays for frequency fine-tuning and a spiral inductor. A method that uses resistor tail biasing for reducing the phase noise and the power consumption has been adopted. The circuit is fully designed in TSMC’s 180 nm technology process. The oscillator output provides three center frequencies of 3.5, 4, 4.5 GHz with good phase noises of -113.784, -116.703 and -126.753 dBc/MHZ at 1 MHz offset, while it dissipates 9mW power energy. The proposed LC VCO not only set a good balance between low phase noise and low power consumption, but it is also a highly desired circuit for multiband wireless transceiver systems, which are the major contributions of this proposed design

WIRELESS ANTENNA MULTIPLEXING USING TUNABLE ANTENNA FOR SPACE APPLICATIONS

Recent development in communication technologies shifts the communication paradigm from point to point to multi-user wireless systems. These developments eased the use of mobile telephone, satellite services, 5G cellular, smart application, and the Internet of Things. The proliferation of mobile devices has necessitated an elaborate mechanism to serve multiple users over a shared communication medium, and a multiplexing approach is introduced to serve this purpose. Multiplexing refers to a method that aims at combining multiple signals into one signal such that each user would be able to extract its desired data upon receiving the multiplexed signal. This spectrum sharing allows wireless operators to maximize the use of their spectrum to accommodate a large number of users over fewer channels. In Space applications, where sensors like temperature, attitude, IR, Magnetic, etc. send information using antennas operate at a different frequency, there is a need to collect all or some of these data using a single device. A wideband antenna requires a filtering process in order to remove unwanted signals that lead to a complex circuit design. Furthermore, the use of multiple antennas ends up with a larger size and additional complexity. Therefore, the tunable antenna is an excellent candidate which provides a perfect solution for such scenarios. A tunable antenna whose frequency characteristics shifted by applying tuning action can be used to operate as a multiplexing device that can collect signals from different surrounding antennas; each operates at a fixed frequency. A system architecture for wireless multiplexing using a tunable antenna is proposed in this project. An electronically tunable antenna using varactor diode as a tuning element is used as the multiplexing device that can collect signals from different surrounding antennas. The system consists of an RF front end and a control circuit/system for wireless multiplexing. The RF front end consists of a tunable antenna, tunable phase shifter, tunable bandpass filter, low noise amplifier, mixer, voltage-controlled oscillator, and an intermediate frequency filter. The control unit comprises a microcontroller, DAC, CMOS oscillator, power module, and a USB interface for communication with custom-built software installed on a PC. The device has functions for control, digital signal processing, and de-multiplexing. The device is fed with an input multiplexed signal, and the de-multiplexed output signals are extracted and displayed on the graphical user interface of the software. Due to the reconfigurability and programmability of the device, it presents a flexible, cost-effective solution for a variety of real-world applications

High Performance LNAs and Mixers for Direct Conversion Receivers in BiCMOS and CMOS Technologies

The trend in cellular chipset design today is to incorporate support for a larger number of frequency bands for each new chipset generation. If the chipset also supports receiver diversity two low noise amplifiers (LNAs) are required for each frequency band. This is however associated with an increase of off-chip components, i.e. matching components for the LNA inputs, as well as complex routing of the RF input signals. If balanced LNAs are implemented the routing complexity is further increased. The first presented work in this thesis is a novel multiband low noise single ended LNA and mixer architecture. The mixer has a novel feedback loop suppressing both second order distortion as well as DC-offset. The performance, verified by Monte Carlo simulations, is sufficient for a WCDMA application. The second presented work is a single ended multiband LNA with programmable integrated matching. The LNA is connected to an on-chip tunable balun generating differential RF signals for a differential mixer. The combination of the narrow band input matching and narrow band balun of the presented LNA is beneficial for suppressing third harmonic downconversion of a WLAN interferer. The single ended architecture has great advantages regarding PCB routing of the RF input signals but is on the other hand more sensitive to common mode interferers, e.g. ground, supply and substrate noise. An analysis of direct conversion receiver requirements is presented together with an overview of different LNA and mixer architectures in both BiCMOS and CMOS technology

Integrated transmitter circuit for multiport reconfigurable antenna

This master’s thesis was a part of an academic research projecta where the target is to design an integrated circuit (IC) to dynamically tune the operating frequency of a transmitter antenna. A multiport antenna model was provided by Prof. Viikari’s group who recently presented a novel idea of multiport antenna tuning. In this concept the multiport antenna feeds are excited with weighted signals having certain amplitudes and phases, thus leading to antenna tuning at the desired operating frequency. However, it is not feasible to dynamically scale the antenna feeding signal amplitudes and phases with discrete electronics. Therefore, the system on chip solution (SoC) approach was studied in this thesis. Initially, the concept was studied on theoretical level and with circuit simulations. The tuning analysis framework was developed to scrutinize the antenna weighted signal characteristics. This analysis provides the two most important specifications for the IC i.e., the accuracy required for on-chip amplitude and phase tuning. For the antenna under consideration, the on chip phase and amplitude tuning system have 6 bit and 3 bit scaling resolutions respectively. The tuning system is designed for a 4-port reconfigurable antenna where each antenna feed has a separate phase tuning and amplitude tuning block. The tuning system was simulated along the 4-port antenna at 2 GHz, and the simulation result validates the multiport tuning concept. This novel integrated tuning system is scalable as well as capable of tuning any reconfigurable multiport antenna

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d