13 research outputs found
Circuit-Level Evaluation of the Generation of Truly Random Bits with Superparamagnetic Tunnel Junctions
Many emerging alternative models of computation require massive numbers of
random bits, but their generation at low energy is currently a challenge. The
superparamagnetic tunnel junction, a spintronic device based on the same
technology as spin torque magnetoresistive random access memory has recently
been proposed as a solution, as this device naturally switches between two easy
to measure resistance states, due only to thermal noise. Reading the state of
the junction naturally provides random bits, without the need of write
operations. In this work, we evaluate a circuit solution for reading the state
of superparamagnetic tunnel junction. We see that the circuit may induce a
small read disturb effect for scaled superparamagnetic tunnel junctions, but
this effect is naturally corrected in the whitening process needed to ensure
the quality of the generated random bits. These results suggest that
superparamagnetic tunnel junctions could generate truly random bits at 20
fJ/bit, including overheads, orders of magnitudes below CMOS-based solutions
GeSe-based Ovonic Threshold Switching Volatile True Random Number Generator
In this paper, we propose and demonstrate a novel technique for true random number generator (TRNG) application using GeSe-based Ovonic threshold switching (OTS) selector devices. The inherent variability in OTS threshold voltage results in a bimodal distribution of on/off states which can be easily converted into digital bits. The experimental evaluation shows that the proposed TRNG enables the generation of high-quality random bits that passed 12 tests in the National Institute of Standards and Technology statistical test suite without complex external circuits for post-processing. The randomness is further evidenced by the prediction rate of ∼50% using machine learning algorithm. Compared with the TRNGs based on non-volatile memories, the volatile nature of OTS avoids the reset operation, thus further simplifying the operation and improving the generation frequency
RRAM Based Random Bit Generation for Hardware Security Applications
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component of this work in other works.Resistive random access memories (RRAMs) have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end processes. The stochastic switching mechanism and intrinsic variability of RRAMs still poses challenges that must be overcome prior to their massive memory commercialization. However, these very same features open a wide range of potential applications for these devices in hardware security. In this context, this work proposes the generation of a random bit by means of simultaneous write operation of two parallel cells so that only one of them unpredictably switches its state. Electrical simulations confirm the strong stochastic behavior and stability of the proposed primitive. Exploiting this fact, a Physical Unclonable Function (PUF) like primitive is implemented based on modified 1 transistor - 1 resistor (1T1R) array structure.Peer ReviewedPostprint (published version
A novel true random number generator based on a stochastic diffusive memristor
The intrinsic variability of switching behavior in memristors has been a major obstacle to their adoption as the next generation universal memory. On the other hand, this natural stochasticity can be valuable for hardware security applications. Here we propose and
demonstrate a novel true random number generator (TRNG) utilizing the stochastic delay time of threshold switching in a Ag:SiO2 diffusive memristor, which exhibits evident advantages in scalability, circuit complexity and power consumption. The random bits generated by the diffusive memristor TRNG passed all 15 NIST randomness tests without any post-processing, a first for memristive-switching TRNGs. Based on nanoparticle
dynamic simulation and analytical estimates, we attributed the stochasticity in delay time to the probabilistic process by which Ag particles detach from a Ag reservoir. This work paves the way for memristors in hardware security applications for the era of Internet of
Things (IoT)
Stochastic Memory Devices for Security and Computing
With the widespread use of mobile computing and internet of things, secured communication and chip authentication have become extremely important. Hardware-based security concepts generally provide the best performance in terms of a good standard of security, low power consumption, and large-area density. In these concepts, the stochastic properties of nanoscale devices, such as the physical and geometrical variations of the process, are harnessed for true random number generators (TRNGs) and physical unclonable functions (PUFs). Emerging memory devices, such as resistive-switching memory (RRAM), phase-change memory (PCM), and spin-transfer torque magnetic memory (STT-MRAM), rely on a unique combination of physical mechanisms for transport and switching, thus appear to be an ideal source of entropy for TRNGs and PUFs. An overview of stochastic phenomena in memory devices and their use for developing security and computing primitives is provided. First, a broad classification of methods to generate true random numbers via the stochastic properties of nanoscale devices is presented. Then, practical implementations of stochastic TRNGs, such as hardware security and stochastic computing, are shown. Finally, future challenges to stochastic memory development are discussed
DESIGN AND TEST OF DIGITAL CIRCUITS AND SYSTEMS USING CMOS AND EMERGING RESISTIVE DEVICES
The memristor is an emerging nano-device. Low power operation, high density, scalability, non-volatility, and compatibility with CMOS Technology have made it a promising technology for memory, Boolean implementation, computing, and logic systems. This dissertation focuses on testing and design of such applications. In particular, we investigate on testing of memristor-based memories, design of memristive implementation of Boolean functions, and reliability and design of neuromorphic computing such as neural network. In addition, we show how to modify threshold logic gates to implement more functions. Although memristor is a promising emerging technology but is prone to defects due to uncertainties in nanoscale fabrication. Fast March tests are proposed in Chapter 2 that benefit from fast write operations. The test application time is reduced significantly while simultaneously reducing the average test energy per cell. Experimental evaluation in 45 nm technology show a speed-up of approximately 70% with a decrease in energy by approximately 40%. DfT schemes are proposed to implement the new test methods. In Chapter 3, an Integer Linear Programming based framework to identify current-mode threshold logic functions is presented. It is shown that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of existing threshold functions is reduced when comparing to the traditional CMOS-based threshold logic implementation. In Chapter 4, a new method to implement threshold logic functions using memristors is presented. This method benefits from the high range of memristor’s resistivity which is used to define different weight values, and reduces significantly the transistor count. The proposed approach implements many more functions as threshold logic gates when comparing to existing implementations. Experimental results in 45 nm technology show that the proposed memristive approach implements threshold logic gates with less area and power consumption. Finally, Chapter 5 focuses on current-based designs for neural networks. CMOS aging impacts the total synaptic current and this impacts the accuracy. Chapter 5 introduces an enhanced memristive crossbar array (MCA) based analog neural network architecture to improve reliability due to the aging effect. A built-in current-based calibration circuit is introduced to restore the total synaptic current. The calibration circuit is a current sensor that receives the ideal reference current for non-aged column and restores the reduced sensed current at each column to the ideal value. Experimental results show that the proposed approach restores the currents with less than 1% precision, and the area overhead is negligible