Memory-Constrained Algorithms for Simple Polygons

A constant-workspace algorithm has read-only access to an input array and may use only O(1) additional words of $O(\log n)$ bits, where $n$ is the size of the input. We assume that a simple $n$-gon is given by the ordered sequence of its vertices. We show that we can find a triangulation of a plane straight-line graph in $O(n^2)$ time. We also consider preprocessing a simple polygon for shortest path queries when the space constraint is relaxed to allow $s$ words of working space. After a preprocessing of $O(n^2)$ time, we are able to solve shortest path queries between any two points inside the polygon in $O(n^2/s)$ time.Comment: Preprint appeared in EuroCG 201

On k-Convex Polygons

We introduce a notion of $k$-convexity and explore polygons in the plane that have this property. Polygons which are \mbox{$k$-convex} can be triangulated with fast yet simple algorithms. However, recognizing them in general is a 3SUM-hard problem. We give a characterization of \mbox{$2$-convex} polygons, a particularly interesting class, and show how to recognize them in \mbox{$O(n \log n)$} time. A description of their shape is given as well, which leads to Erd\H{o}s-Szekeres type results regarding subconfigurations of their vertex sets. Finally, we introduce the concept of generalized geometric permutations, and show that their number can be exponential in the number of \mbox{$2$-convex} objects considered.Comment: 23 pages, 19 figure

External-Memory Algorithms for Processing Line Segments in Geographic Information Systems

The original publication is available at www.springerlink.comIn the design of algorithms for large-scale applications it is essential to consider the problem of minimizing I/O communication. Geographical information systems (GIS) are good examples of such large-scale applications as they frequently handle huge amounts of spatial data. In this paper we develop e cient new external-memory algorithms for a number of important problems involving line segments in the plane, including trapezoid decomposition, batched planar point location, triangulation, red-blue line segment intersection reporting, and general line segment intersection reporting. In GIS systems, the rst three problems are useful for rendering and modeling, and the latter two are frequently used for overlaying maps and extracting information from them

Improved algorithms for ear-clipping triangulation

We consider the problem of improving ear-slicing algorithm for triangulating a simple polygon. We propose two variations of ear-slicing technique for generating “good-quality” triangulation. The first approach is based on searching for the best triangle along the boundary. The second approach considers polygon partitioning on a pre-process before applying the ear-slicing. Experimental investigation reveals that both approaches yield better quality triangulation than the standard ear-slicing method

Modification of Fournier and Montuno's Triangulation Algorithm for Simple Polygons�

Triangulation of a simple polygon is an important part of the application of geometry problems in computer graphics. A conventional triangulation algorithm runs in O(n2). Faster tringulation methods have been developed but these methods are more complicated. A simpler triangulation method was developed by Fournier and Montuno, which runs in O(n log n). The modified triangulation algorithm presented here compares favorably with the Fournier and Montuno's triangulation algorithm and is simpler in the sense of elimination of recursion. The Fournier and Montuno's triangulation algorithm and the modified triangulation algorithm are implemented using c. The performance of the two algorithms is analyzed using various data.Computer Scienc

VLSI Routing for Advanced Technology

Routing is a major step in VLSI design, the design process of complex integrated circuits (commonly known as chips). The basic task in routing is to connect predetermined locations on a chip (pins) with wires which serve as electrical connections. One main challenge in routing for advanced chip technology is the increasing complexity of design rules which reflect manufacturing requirements. In this thesis we investigate various aspects of this challenge. First, we consider polygon decomposition problems in the context of VLSI design rules. We introduce different width notions for polygons which are important for width-dependent design rules in VLSI routing, and we present efficient algorithms for computing width-preserving decompositions of rectilinear polygons into rectangles. Such decompositions are used in routing to allow for fast design rule checking. A main contribution of this thesis is an O(n) time algorithm for computing a decomposition of a simple rectilinear polygon with n vertices into O(n) rectangles, preseverving two-dimensional width. Here the two-dimensional width at a point of the polygon is defined as the edge length of a largest square that contains the point and is contained in the polygon. In order to obtain these results we establish a connection between such decompositions and Voronoi diagrams. Furthermore, we consider implications of multiple patterning and other advanced design rules for VLSI routing. The main contribution in this context is the detailed description of a routing approach which is able to manage such advanced design rules. As a main algorithmic concept we use multi-label shortest paths where certain path properties (which model design rules) can be enforced by defining labels assigned to path vertices and allowing only certain label transitions. The described approach has been implemented in BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics, University of Bonn, in cooperation with IBM. We present experimental results confirming that a flow combining BonnRoute and an external cleanup step produces far superior results compared to an industry standard router. In particular, our proposed flow runs more than twice as fast, reduces the via count by more than 20%, the wiring length by more than 10%, and the number of remaining design rule errors by more than 60%. These results obtained by applying our multiple patterning approach to real-world chip instances provided by IBM are another main contribution of this thesis. We note that IBM uses our proposed combined BonnRoute flow as the default tool for signal routing