2,104 research outputs found

    Transputer control of a flexible robot link

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    The applicability of transputers in control systems is investigated. This is done by implementing a controller for a flexible robot arm with one degree of freedom on a system consisting of an IBM-AT and four transputers. It is found that a control system with transputers offers a great improvement compared with conventional digital control systems. Transputers can solve the common problem in control practice, i.e. having very sophisticted controllers but not being able to implement them because they need too much computing time. However, transputers are not an optimal solution for more sophisticated control systems because of shortcomings in the scheduling mechanism

    RTNN: The new parallel machine in Zaragoza

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    I report on the development of RTNN, a parallel computer designed as a 4^4 hypercube of 256 T9000 transputer nodes, each with 8 MB memory. The peak performance of the machine is expected to be 2.5 Gflops.Comment: 10 pages PostScript, including 5 figures. Write-up (June 1995) of talk at the International Workshop ``QCD on Massively Parallel Computers'', Yamagata, Japan, 16-18 March 1995. To appear in the Proceedings, Suppl. Progr. Theor. Phys. (Kyoto

    Emulating Digital Logic using Transputer Networks (Very High Parallelism = Simplicity = Performance)

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    Modern VLSI technology has changed the economic rules by which the balance between processing power, memory and communications is decided in computing systems. This will have a profound impact on the design rules for the controlling software. In particular, the criteria for judging efficiency of the algorithms will be somewhat different. This paper explores some of these implications through the development of highly parallel and highly distributable algorithms based on occam and transputer networks. The major results reported are a new simplicity for software designs, a corresponding ability to reason (formally and informally) about their properties, the reusability of their components and some real performance figures which demonstrate their practicality. Some guidelines to assist in these designs are also given. As a vehicle for discussion, an interactive simulator is developed for checking the functional and timing characteristics of digital logic circuits of arbitrary complexity

    HTML Macros -- Easing the Construction and Maintenance of Web Texts

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    Authoring and maintaining large collections of Web texts is a cumbersome, error-prone and time-consuming business. Ongoing development of courseware for the High Performance Computing Consortium (HPCC) TLTP has only helped to emphasise these problems. Courseware requires the application of a coherent document layout (templates) for each page, and also the use of standard icons with a consistent functionality, in order to create a constant look and feel throughout the material. This provides the user with an environment where he or she can access new pages, and instantly recognise the format used, making the extraction of the information on the page much quicker, and less immediately confusing. This paper describes a system that was developed at UKC to provide a solution to the above problems via the introduction of HTML macros. These macros can be used to provide a standard document layout with a consistent look and feel, as well as tools to ease user navigation. The software is written in Perl, and achieves macro expansion and replacement using the Common Gateway Interface (CGI) and filtering the HTML source. Using macros in your HTML results in your document source code being shorter, more robust, and more powerful. Webs of documents can be built extremely fast and maintenance is made much simpler. Keywords: Authoring, Automation Tools, Perl filters for HTML, Teaching and learning on the We

    Multiprocessor graphics computation and display using transputers

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    A package of two-dimensional graphics routines was developed to run on a transputer-based parallel processing system. These routines were designed to enable applications programmers to easily generate and display results from the transputer network in a graphic format. The graphics procedures were designed for the lowest possible network communication overhead for increased performance. The routines were designed for ease of use and to present an intuitive approach to generating graphics on the transputer parallel processing system

    Fault-tolerant computer architecture based on INMOS transputer processor

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    Redundant processing was used for several years in mission flight systems. In these systems, more than one processor performs the same task at the same time but only one processor is actually in real use. A fault-tolerance computer architecture based on the features provided by INMOS Transputers is presented. The Transputer architecture provides several communication links that allow data and command communication with other Transputers without the use of a bus. Additionally the Transputer allows the use of parallel processing to increase the system speed considerably. The processor architecture consists of three processors working in parallel keeping all the processors at the same operational level but only one processor is in real control of the process. The design allows each Transputer to perform a test to the other two Transputers and report the operating condition of the neighboring processors. A graphic display was developed to facilitate the identification of any problem by the user

    The 3D laser radar vision processor system

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    Loral Defense Systems (LDS) developed a 3D Laser Radar Vision Processor system capable of detecting, classifying, and identifying small mobile targets as well as larger fixed targets using three dimensional laser radar imagery for use with a robotic type system. This processor system is designed to interface with the NASA Johnson Space Center in-house Extra Vehicular Activity (EVA) Retriever robot program and provide to it needed information so it can fetch and grasp targets in a space-type scenario

    An occam Style Communications System for UNIX Networks

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    This document describes the design of a communications system which provides occam style communications primitives under a Unix environment, using TCP/IP protocols, and any number of other protocols deemed suitable as underlying transport layers. The system will integrate with a low overhead scheduler/kernel without incurring significant costs to the execution of processes within the run time environment. A survey of relevant occam and occam3 features and related research is followed by a look at the Unix and TCP/IP facilities which determine our working constraints, and a description of the T9000 transputer's Virtual Channel Processor, which was instrumental in our formulation. Drawing from the information presented here, a design for the communications system is subsequently proposed. Finally, a preliminary investigation of methods for lightweight access control to shared resources in an environment which does not provide support for critical sections, semaphores, or busy waiting, is made. This is presented with relevance to mutual exclusion problems which arise within the proposed design. Future directions for the evolution of this project are discussed in conclusion

    Efficient computation of aerodynamic influence coefficients for aeroelastic analysis on a transputer network

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    Aeroelastic analysis is multi-disciplinary and computationally expensive. Hence, it can greatly benefit from parallel processing. As part of an effort to develop an aeroelastic capability on a distributed memory transputer network, a parallel algorithm for the computation of aerodynamic influence coefficients is implemented on a network of 32 transputers. The aerodynamic influence coefficients are calculated using a 3-D unsteady aerodynamic model and a parallel discretization. Efficiencies up to 85 percent were demonstrated using 32 processors. The effect of subtask ordering, problem size, and network topology are presented. A comparison to results on a shared memory computer indicates that higher speedup is achieved on the distributed memory system
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