The state of peer-to-peer network simulators

Networking research often relies on simulation in order to test and evaluate new ideas. An important requirement of this process is that results must be reproducible so that other researchers can replicate, validate and extend existing work. We look at the landscape of simulators for research in peer-to-peer (P2P) networks by conducting a survey of a combined total of over 280 papers from before and after 2007 (the year of the last survey in this area), and comment on the large quantity of research using bespoke, closed-source simulators. We propose a set of criteria that P2P simulators should meet, and poll the P2P research community for their agreement. We aim to drive the community towards performing their experiments on simulators that allow for others to validate their results

advligorts: The Advanced LIGO Real-Time Digital Control and Data Acquisition System

The Advanced LIGO detectors are sophisticated opto-mechanical devices. At the core of their operation is feedback control. The Advanced LIGO project developed a custom digital control and data acquisition system to handle the unique needs of this new breed of astronomical detector. The advligorts is the software component of this system. This highly modular and extensible system has enabled the unprecedented performance of the LIGO instruments, and has been a vital component in the direct detection of gravitational waves

Analog Content-Addressable Memory from Complementary FeFETs

To address the increasing computational demands of artificial intelligence (AI) and big data, compute-in-memory (CIM) integrates memory and processing units into the same physical location, reducing the time and energy overhead of the system. Despite advancements in non-volatile memory (NVM) for matrix multiplication, other critical data-intensive operations, like parallel search, have been overlooked. Current parallel search architectures, namely content-addressable memory (CAM), often use binary, which restricts density and functionality. We present an analog CAM (ACAM) cell, built on two complementary ferroelectric field-effect transistors (FeFETs), that performs parallel search in the analog domain with over 40 distinct match windows. We then deploy it to calculate similarity between vectors, a building block in the following two machine learning problems. ACAM outperforms ternary CAM (TCAM) when applied to similarity search for few-shot learning on the Omniglot dataset, yielding projected simulation results with improved inference accuracy by 5%, 3x denser memory architecture, and more than 100x faster speed compared to central processing unit (CPU) and graphics processing unit (GPU) per similarity search on scaled CMOS nodes. We also demonstrate 1-step inference on a kernel regression model by combining non-linear kernel computation and matrix multiplication in ACAM, with simulation estimates indicating 1,000x faster inference than CPU and GPU

Self-healing concepts involving fine-grained redundancy for electronic systems

The start of the digital revolution came through the metal-oxide-semiconductor field-effect transistor (MOSFET) in 1959 followed by massive integration onto a silicon die by means of constant down scaling of individual components. Digital systems for certain applications require fault-tolerance against faults caused by temporary or permanent influence. The most widely used technique is triple module redundancy (TMR) in conjunction with a majority voter, which is regarded as a passive fault mitigation strategy. Design by functional resilience has been applied to circuit structures for increased fault-tolerance and towards self-diagnostic triggered self-healing. The focus of this thesis is therefore to develop new design strategies for fault detection and mitigation within transistor, gate and cell design levels. The research described in this thesis makes three contributions. The first contribution is based on adding fine-grained transistor level redundancy to logic gates in order to accomplish stuck-at fault-tolerance. The objective is to realise maximum fault-masking for a logic gate with minimal added redundant transistors. In the case of non-maskable stuck-at faults, the gate structure generates an intrinsic indication signal that is suitable for autonomous self-healing functions. As a result, logic circuitry utilising this design is now able to differentiate between gate faults and faults occurring in inter-gate connections. This distinction between fault-types can then be used for triggering selective self-healing responses. The second contribution is a logic matrix element which applies the three core redundancy concepts of spatial- temporal- and data-redundancy. This logic structure is composed of quad-modular redundant structures and is capable of selective fault-masking and localisation depending of fault-type at the cell level, which is referred to as a spatiotemporal quadded logic cell (QLC) structure. This QLC structure has the capability of cellular self-healing. Through the combination of fault-tolerant and masking logic features the QLC is designed with a fault-behaviour that is equal to existing quadded logic designs using only 33.3% of the equivalent transistor resources. The inherent self-diagnosing feature of QLC is capable of identifying individual faulty cells and can trigger self-healing features. The final contribution is focused on the conversion of finite state machines (FSM) into memory to achieve better state transition timing, minimal memory utilisation and fault protection compared to common FSM designs. A novel implementation based on content-addressable type memory (CAM) is used to achieve this. The FSM is further enhanced by creating the design out of logic gates of the first contribution by achieving stuck-at fault resilience. Applying cross-data parity checking, the FSM becomes equipped with single bit fault detection and correction

On the number of limit cycles in asymmetric neural networks

The comprehension of the mechanisms at the basis of the functioning of complexly interconnected networks represents one of the main goals of neuroscience. In this work, we investigate how the structure of recurrent connectivity influences the ability of a network to have storable patterns and in particular limit cycles, by modeling a recurrent neural network with McCulloch-Pitts neurons as a content-addressable memory system. A key role in such models is played by the connectivity matrix, which, for neural networks, corresponds to a schematic representation of the "connectome": the set of chemical synapses and electrical junctions among neurons. The shape of the recurrent connectivity matrix plays a crucial role in the process of storing memories. This relation has already been exposed by the work of Tanaka and Edwards, which presents a theoretical approach to evaluate the mean number of fixed points in a fully connected model at thermodynamic limit. Interestingly, further studies on the same kind of model but with a finite number of nodes have shown how the symmetry parameter influences the types of attractors featured in the system. Our study extends the work of Tanaka and Edwards by providing a theoretical evaluation of the mean number of attractors of any given length $L$ for different degrees of symmetry in the connectivity matrices.Comment: 35 pages, 12 figure

A ferrofluid based neural network: design of an analogue associative memory

We analyse an associative memory based on a ferrofluid, consisting of a system of magnetic nano-particles suspended in a carrier fluid of variable viscosity subject to patterns of magnetic fields from an array of input and output magnetic pads. The association relies on forming patterns in the ferrofluid during a trainingdphase, in which the magnetic dipoles are free to move and rotate to minimize the total energy of the system. Once equilibrated in energy for a given input-output magnetic field pattern-pair the particles are fully or partially immobilized by cooling the carrier liquid. Thus produced particle distributions control the memory states, which are read out magnetically using spin-valve sensors incorporated in the output pads. The actual memory consists of spin distributions that is dynamic in nature, realized only in response to the input patterns that the system has been trained for. Two training algorithms for storing multiple patterns are investigated. Using Monte Carlo simulations of the physical system we demonstrate that the device is capable of storing and recalling two sets of images, each with an accuracy approaching 100%.Comment: submitted to Neural Network

Towards a Taxonomy of Inter-network Architectures

Over the past decade, research on network architecture design has intensified. However, contributions to the field have mainly been idiosyncratic and architectural descriptions remain idiomatic. This state of affairs has led to the emergence of a large body of network architecture proposals with no clear indication of their compatibility points, their cross similarities, and their differences. Thus, a taxonomy of network architectures that provides a framework for better understanding, organizing, and thinking about the complex architecture design space would be a timely contribution. This paper presents a first step in that direction by attempting a classification based on the architecture\u27s information model. The taxonomy is applied to a special network architecture highlighting its descriptive and classification powers

The "MIND" Scalable PIM Architecture

MIND (Memory, Intelligence, and Network Device) is an advanced parallel computer architecture for high performance computing and scalable embedded processing. It is a Processor-in-Memory (PIM) architecture integrating both DRAM bit cells and CMOS logic devices on the same silicon die. MIND is multicore with multiple memory/processor nodes on each chip and supports global shared memory across systems of MIND components. MIND is distinguished from other PIM architectures in that it incorporates mechanisms for efficient support of a global parallel execution model based on the semantics of message-driven multithreaded split-transaction processing. MIND is designed to operate either in conjunction with other conventional microprocessors or in standalone arrays of like devices. It also incorporates mechanisms for fault tolerance, real time execution, and active power management. This paper describes the major elements and operational methods of the MIND architecture

Care 3, Phase 1, volume 1

A computer program to aid in accessing the reliability of fault tolerant avionics systems was developed. A simple mathematical expression was used to evaluate the reliability of any redundant configuration over any interval during which the failure rates and coverage parameters remained unaffected by configuration changes. Provision was made for convolving such expressions in order to evaluate the reliability of a dual mode system. A coverage model was also developed to determine the various relevant coverage coefficients as a function of the available hardware and software fault detector characteristics, and subsequent isolation and recovery delay statistics

INTEGRATED CIRCUITS FOR HIGH ENERGY PHYSICS EXPERIMETNS

Integrated Circuits are used in most people\u2019s lives in the modern societies. An important branch of research and technology is focused on Integrated Circuit (IC) design, fabrication, and their efficient applications; moreover most of these activities are about commercial productions with applications in ambient environment. However the ICs play very important role in very advance research fields, as Astronomy or High Energy Physics experiments, with absolutely extreme environments which require very interdisciplinary research orientations and innovative solutions. For example, the Fast TracKer (FTK) electronic system, which is an important part of triggering system in ATLAS experiment at European Organization for Nuclear Research (CERN), in every second of experiment selects 200 interesting events among 40 millions of total events due to collision of accelerated protons. The FTK function is based on ICs which work as Content Addressable Memory (CAM). A CAM compares the income data with stored data and gives the addresses of matching data as an output. The amount of calculation in FTK system is out of capacity of commercial ICs even in very advanced technologies, therefore the development of innovative ICs is required. The high power consumption due to huge amount of calculation was an important limitation which is overcome by an innovative architecture of CAM in this dissertation. The environment of ICs application in astrophysics and High Energy Physics experiments is different from commercial ICs environment because of high amount of radiation. This fact started to get seriously attention after the first \u201cTelstar I\u201d satellite failure because of electronic damages due to radiation effects in space, and opened a new field of research mostly about radiation hard electronics. The multidisciplinary research in radiation hard electronic field is about radiation effects on semiconductors and ICs, deep understanding about the radiation in the extreme environments, finding alternative solutions to increase the radiation tolerance of electronic components, and development of new simulation method and test techniques. Chapter 2 of this dissertation is about the radiation effects on Silicon and ICs. Moreover, In this chapter, the terminologies of radiation effects on ICs are explained. In chapter 3, the space and high energy physics experiments environments, which are two main branches of radiation hard electronics research, are studied. The radiation tolerance in on-chip circuits is achieving by two kinds of methodology: Radiation Hardening By Process (RHBP) and Radiation Hardening By Design (RHBD). RHBP is achieved by changing the conventional fabrication process of commercial ICs. RHBP is very expensive so it is out of budget for academic research, and in most cases it is exclusive for military application, with very restricted rules which make the access of non-military organizations impossible. RHBD with conventional process is the approach of radiation hard IC design in this dissertation. RHBD at hardware level can be achieved in different ways: \u2022 System level RHBD: radiation hardening at system level is achieved by algorithms which are able to extract correct data using redundant information. \u2022Architecture level RHBD: some hardware architectures are able to prevent of lost data or mitigate the radiation effects on stored data without interfacing of software. Error Correction Code (ECC) circuits and Dual Interlocked storage CEll (DICE) architecture are two examples of RHBD at architecture level. \u2022 Circuit level RHBD: at circuit level, some structures are avoided or significantly reduced. For example, feedback loops with high gain are very sensitive to radiation effects. \u2022 Layout level RHBD: there are also different solutions in layout design level to increase the radiation tolerance of circuits. Specific shapes of transistor design, optimization of the physical distance between redundant data and efficient polarization of substrate are some techniques commonly used to increase significantly the radiation tolerance of ICs. An innovative radiation hard Static Random Access Memory (SRAM), designed in three versions, is presented in chapter 4. The radiation hardening is achieved by RHBD approach simultaneously at architecture, circuit and layout levels. Complementary Metal-Oxide-Semiconductor (CMOS) 65 nm is the technology of design and the prototype chip is fabricated at Taiwan Semiconductor Manufacturing Company (TSMC). Chapter 5 is about the development of simulation models that can help to predict the radiation effect in the behavior of SRAM block. The setup system developed to characterize the radiation hard SRAM prototype chip is presented in Chapter 5. The setup system gives the possibility of testing the prototype exposed under radiation in a vacuum chamberand regular laboratory environment. Chapter 6 is about the contribution of this dissertation on FTK project and the conclusion of all research activities is shown in the final part of this dissertation. The research activities of this dissertation in supported by Italian National Institute for Nuclear Physics (INFN) as part of CHIPIX65 project and RD53 collaboration at CERN