Low Power Decoding Circuits for Ultra Portable Devices

A wide spread of existing and emerging battery driven wireless devices do not necessarily demand high data rates. Rather, ultra low power, portability and low cost are the most desired characteristics. Examples of such applications are wireless sensor networks (WSN), body area networks (BAN), and a variety of medical implants and health-care aids. Being small, cheap and low power for the individual transceiver nodes, let those to be used in abundance in remote places, where access for maintenance or recharging the battery is limited. In such scenarios, the lifetime of the battery, in most cases, determines the lifetime of the individual nodes. Therefore, energy consumption has to be so low that the nodes remain operational for an extended period of time, even up to a few years. It is known that using error correcting codes (ECC) in a wireless link can potentially help to reduce the transmit power considerably. However, the power consumption of the coding-decoding hardware itself is critical in an ultra low power transceiver node. Power and silicon area overhead of coding-decoding circuitry needs to be kept at a minimum in the total energy and cost budget of the transceiver node. In this thesis, low power approaches in decoding circuits in the framework of the mentioned applications and use cases are investigated. The presented work is based on the 65nm CMOS technology and is structured in four parts as follows: In the first part, goals and objectives, background theory and fundamentals of the presented work is introduced. Also, the ECC block in coordination with its surrounding environment, a low power receiver chain, is presented. Designing and implementing an ultra low power and low cost wireless transceiver node introduces challenges that requires special considerations at various levels of abstraction. Similarly, a competitive solution often occurs after a conclusive design space exploration. The proposed decoder circuits in the following parts are designed to be embedded in the low power receiver chain, that is introduced in the first part. Second part, explores analog decoding method and its capabilities to be embedded in a compact and low power transceiver node. Analog decod- ing method has been theoretically introduced over a decade ago that followed with early proof of concept circuits that promised it to be a feasible low power solution. Still, with the increased popularity of low power sensor networks, it has not been clear how an analog decoding approach performs in terms of power, silicon area, data rate and integrity of calculations in recent technologies and for low data rates. Ultra low power budget, small size requirement and more relaxed demands on data rates suggests a decoding circuit with limited complexity. Therefore, the four-state (7,5) codes are considered for hardware implementation. Simulations to chose the critical design factors are presented. Consequently, to evaluate critical specifications of the decoding circuit, three versions of analog decoding circuit with different transistor dimensions fabricated. The measurements results reveal different trade-off possibilities as well as the potentials and limitations of the analog decoding approach for the target applications. Measurements seem to be crucial, since the available computer-aided design (CAD) tools provide limited assistance and precision, given the amount of calculations and parameters that has to be included in the simulations. The largest analog decoding core (AD1) takes 0.104mm2 on silicon and the other two (AD2 and AD3) take 0.035mm2 and 0.015mm2, respectively. Consequently, coding gain in trade-off with silicon area and throughput is presented. The analog decoders operate with 0.8V supply. The achieved coding gain is 2.3 dB at bit error rates (BER)=0.001 and 10 pico-Joules per bit (pJ/b) energy efficiency is reached at 2 Mbps. Third part of this thesis, proposes an alternative low power digital decoding approach for the same codes. The desired compact and low power goal has been pursued by designing an equivalent digital decoding circuit that is fabricated in 65nm CMOS technology and operates in low voltage (near-threshold) region. The architecture of the design is optimized in system and circuit levels to propose a competitive digital alternative. Similarly, critical specifications of the decoder in terms of power, area, data rate (speed) and integrity are reported according to the measurements. The digital implementation with 0.11mm2 area, consumes minimum energy at 0.32V supply which gives 9 pJ/b energy efficiency at 125 kb/s and 2.9 dB coding gain at BER=0.001. The forth and last part, compares the proposed design alternatives based on the fabricated chips and the results attained from the measurements to conclude the most suitable solution for the considered target applications. Advantages and disadvantages of both approaches are discussed. Possible extensions of this work is introduced as future work

Deconvolution of Quantized-Input Linear Systems: An Information-Theoretic Approach

The deconvolution problem has been drawing the attention of mathematicians, physicists and engineers since the early sixties. Ubiquitous in the applications, it consists in recovering the unknown input of a convolution system from noisy measurements of the output. It is a typical instance of inverse, ill-posed problem: the existence and uniqueness of the solution are not assured and even small perturbations in the data may cause large deviations in the solution. In the last fifty years, a large amount of estimation techniques have been proposed by different research communities to tackle deconvolution, each technique being related to a peculiar engineering application or mathematical set. In many occurrences, the unknown input presents some known features, which can be exploited to develop ad hoc algorithms. For example, prior information about regularity and smoothness of the input function are often considered, as well as the knowledge of a probabilistic distribution on the input source: the estimation techniques arising in different scenarios are strongly diverse. Less effort has been dedicated to the case where the input is known to be affected by discontinuities and switches, which is becoming an important issue in modern technologies. In fact, quantized signals, that is, piecewise constant functions that can assume only a finite number of values, are nowadays widespread in the applications, given the ongoing process of digitization concerning most of information and communication systems. Moreover, hybrid systems are often encountered, which are characterized by the introduction of quantized signals into physical, analog communication channels. Motivated by such consideration, this dissertation is devoted to the study of the deconvolution of continuous systems with quantized input; in particular, our attention will be focused on linear systems. Given the discrete nature of the input, we will show that the whole problem can be interpreted as a paradigmatic digital transmission problem and we will undertake an Information-theoretic approach to tackle it. The aim of this dissertation is to develop suitable deconvolution algorithms for quantized-input linear systems, which will be derived from known decoding procedures, and to test them in different scenarios. Much consideration will be given to the theoretical analysis of these algorithms, whose performance will be rigorously described in mathematical terms

Deconvolution of Quantized-Input Linear Systems : an Information-Theoretic Approach

The deconvolution problem has been drawing the attention of mathematicians, physicists and engineers since the early sixties. Ubiquitous in the applications, it consists in recovering the unknown input of a convolution system from noisy measurements of the output. It is a typical instance of inverse, ill-posed problem: the existence and uniqueness of the solution are not assured and even small perturbations in the data may cause large deviations in the solution. In the last fifty years, a large amount of estimation techniques have been proposed by di fferent research communities to tackle deconvolution, each technique being related to a peculiar engineering application or mathematical set. In many occurrences, the unknown input presents some known features, which can be exploited to develop ad hoc algorithms. For example, prior information about regularity and smoothness of the input function are often considered, as well as the knowledge of a probabilistic distribution on the input source: the estimation techniques arising in diff erent scenarios are strongly diverse. Less eff ort has been dedicated to the case where the input is known to be aff ected by discontinuities and switches, which is becoming an important issue in modern technologies. In fact, quantized signals, that is, piecewise constant functions that can assume only a fi nite number of values, are nowadays widespread in the applications, given the ongoing process of digitization concerning most of information and communication systems. Moreover, hybrid systems are often encountered, which are characterized by the introduction of quantized signals into physical, analog communication channels. Motivated by such consideration, this dissertation is devoted to the study of the deconvolution of continuous systems with quantized input; in particular, our attention will be focused on linear systems. Given the discrete nature of the input, we will show that the whole problem can be interpreted as a paradigmatic digital transmission problem and we will undertake an Information-theoretic approach to tackle it. The aim of this dissertation is to develop suitable deconvolution algorithms for quantized-input linear systems, which will be derived from known decoding procedures, and to test them in diff erent scenarios. Much consideration will be given to the theoretical analysis of these algorithms, whose performance will be rigorously described in mathematical terms

Coherent receiver design and analysis for interleaved division multiple access (IDMA)

This thesis discusses a new multiuser detection technique for cellular wireless communications. Multiuser communications is critical in cellular systems as multiple terminals (users) transmit to base stations (or wireless infrastructure). Efficient receiver methods are needed to maximise the performance of these links and maximise overall throughput and coverage while minimising inter-cell interference. Recently a new technique, Interleave-Division Multiple Access (IDMA), was developed as a variant of direct-sequence code division multiple access (DS-CDMA). In this new scheme users are separated by user specific interleavers, and each user is allocated a low rate code. As a result, the bandwidth expansion is devoted to the low rate code and not weaker spreading codes. IDMA has shown to have significant performance gains over traditional DS-CDMA with a modest increase in complexity. The literature on IDMA primarily focuses on the design of low rate forward error correcting (FEC) codes, as well as channel estimation. However, the practical aspects of an IDMA receiver such as timing acquisition, tracking, block asynchronous detection, and cellular analysis are rarely studied. The objective of this thesis is to design and analyse practical synchronisation, detection and power optimisation techniques for IDMA systems. It also, for the first time, provides a novel analysis and design of a multi-cell system employing a general multiuser receiver. These tools can be used to optimise and evaluate the performance of an IDMA communication system. The techniques presented in this work can be easily employed for DS-CDMA or other multiuser receiver designs with slight modification. Acquisition and synchronisation are essential processes that a base-station is required to perform before user's data can be detected and decoded. For high capacity IDMA systems, which can be heavily loaded and operate close to the channel capacity, the performance of acquisition and tracking can be severely affected by multiple access interference as well as severe drift. This thesis develops acquisition and synchronisation algorithms which can cope with heavy multiple access interference as well as high levels of drift. Once the timing points have been estimated for an IDMA receiver the detection and decoding process can proceed. An important issue with uplink systems is the alignment of frame boundaries for efficient detection. This thesis demonstrates how a fully asynchronous system can be modelled for detection. This thesis presents a model for the frame asynchronous IDMA system, and then develops a maximum likelihood receiver for the proposed system. This thesis develops tools to analyse and optimise IDMA receivers. The tools developed are general enough to be applied to other multiuser receiver techniques. The conventional EXIT chart analysis of unequal power allocated multiuser systems use an averaged EXIT chart analysis for all users to reduce the complexity of the task. This thesis presents a multidimensional analysis for power allocated IDMA, and shows how it can be utilised in power optimisation. Finally, this work develops a novel power zoning technique for multicell multiuser receivers using the optimised power levels, and illustrates a particular example where there is a 50% capacity improvement using the proposed scheme. -- provided by Candidate

On the Impact of Phase Noise in Communication Systems –- Performance Analysis and Algorithms

The mobile industry is preparing to scale up the network capacity by a factor of 1000x in order to cope with the staggering growth in mobile traffic. As a consequence, there is a tremendous pressure on the network infrastructure, where more cost-effective, flexible, high speed connectivity solutions are being sought for. In this regard, massive multiple-input multiple-output (MIMO) systems, and millimeter-wave communication systems are new physical layer technologies, which promise to facilitate the 1000 fold increase in network capacity. However, these technologies are extremely prone to hardware impairments like phase noise caused by noisy oscillators. Furthermore, wireless backhaul networks are an effective solution to transport data by using high-order signal constellations, which are also susceptible to phase noise impairments. Analyzing the performance of wireless communication systems impaired by oscillator phase noise, and designing systems to operate efficiently in strong phase noise conditions are critical problems in communication theory. The criticality of these problems is accentuated with the growing interest in new physical layer technologies, and the deployment of wireless backhaul networks. This forms the main motivation for this thesis where we analyze the impact of phase noise on the system performance, and we also design algorithms in order to mitigate phase noise and its effects. First, we address the problem of maximum a posteriori (MAP) detection of data in the presence of strong phase noise in single-antenna systems. This is achieved by designing a low-complexity joint phase-estimator data-detector. We show that the proposed method outperforms existing detectors, especially when high order signal constellations are used. Then, in order to further improve system performance, we consider the problem of optimizing signal constellations for transmission over channels impaired by phase noise. Specifically, we design signal constellations such that the error rate performance of the system is minimized, and the information rate of the system is maximized. We observe that these optimized constellations significantly improve the system performance, when compared to conventional constellations, and those proposed in the literature. Next, we derive the MAP symbol detector for a MIMO system where each antenna at the transceiver has its own oscillator. We propose three suboptimal, low-complexity algorithms for approximately implementing the MAP symbol detector, which involve joint phase noise estimation and data detection. We observe that the proposed techniques significantly outperform the other algorithms in prior works. Finally, we study the impact of phase noise on the performance of a massive MIMO system, where we analyze both uplink and downlink performances. Based on rigorous analyses of the achievable rates, we provide interesting insights for the following question: how should oscillators be connected to the antennas at a base station, which employs a large number of antennas

Integrating spinal codes into wireless systems

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student-submitted PDF version of thesis.Includes bibliographical references (p. 85-88).Rateless spinal codes [47] promise performance gains for future wireless systems. These gains can be realized in the form of higher data rates, longer operational ranges, reduced power consumption, and greater reliability. This is due in part to the manner in which rateless codes exploit the instantaneous characteristics of the wireless medium, including unpredictable fluctuations. By contrast, traditional rated codes can accommodate variability only by making overly conservative assumptions. Before spinal codes reach practical deployment, they must be integrated into the networking stacks of real devices, and they must be instantiated in compact, ecient silicon. This thesis addresses fundamental challenges in each of these two areas, covering a body of work reported in previous publications by this author and others [27, 26]. On the networking side, this thesis explores a rateless analogue of link-layer retransmission schemes, capturing the idea of rate adaptation and generalizing the approach of hybrid ARQ/incremental redundancy systems such as LTE [29]. On the silicon side, this thesis presents the development of a VLSI architecture that exploits the inherent parallelism of the spinal decoder.by Peter Anthony Iannucci.S.M

Beamforming for OFDM based hybrid terrestrial satellite mobile system

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