Biased Aspirations and Social Inequality at School: Evidence from French Teenagers

This paper provides empirical evidence on how aspirations are formed and affect individual behavior, decisions, and paths in the context of education. Using unique data on aspirations, academic performance and actual track assignment to high school of French ninth graders, we show that low-SES students have lower aspirations than their equally-achieving high-SES classmates, and that track assignments to high school the next year are even more unequal due to dysfunctional dynamics: first, both low aspirations and low SES are associated with slower academic progress over the year. Second, aspirations and parental SES play a role in track assignment independent of one’s academic performance. Our results suggest that, in France, an aspirational trap at school contributes to the poverty trap, leading to the perpetuation of social inequalities

Faster Goal-Oriented Shortest Path Search for Bulk and Incremental Detailed Routing

We develop new algorithmic techniques for VLSI detailed routing. First, we improve the goal-oriented version of Dijkstra's algorithm to find shortest paths in huge incomplete grid graphs with edge costs depending on the direction and the layer, and possibly on rectangular regions. We devise estimates of the distance to the targets that offer better trade-offs between running time and quality than previously known methods, leading to an overall speed-up. Second, we combine the advantages of the two classical detailed routing approaches - global shortest path search and track assignment with local corrections - by treating input wires (such as the output of track assignment) as reservations that can be used at a discount by the respective net. We show how to implement this new approach efficiently

The quality of school track assignment decisions by teachers

We study the quality of secondary school track assignment decisions in the Netherlands, using a regression discontinuity design. In 6th grade, primary school teachers assign each student to a secondary school track. If a student scores above a track-specific cutoff on the standardized end-of-primary education test, the teacher can upwardly revise this assignment. By comparing students just left and right of these cutoffs, we find that between 50-90% of the students are "trapped in track": these students are on the high track after four years, only if they started on the high track in first year. The remaining (minority of) students are "always low": they are always on the low track after four years, independently of where they started. These proportions hold for students near the cutoffs that shift from the low to the high track in first year by scoring above the cutoff. Hence, for a majority of these students the initial (unrevised) track assignment decision is too low. The results replicate across most of the secondary school tracks, from the vocational to the academic tracks, and stand out against an education system with a lot of upward and downward track mobility

Research on Methods for Very Large Scale Integration Track Assignment Routing

Routing is a crucial stage in the physical design of Very Large Scale Integration (VLSI) circuits, comprising three phases: global routing, track assignment routing, and detailed routing. With the development of VLSI circuits, scholars have proposed various track assignment routing algorithms. However, improving the efficiency of track assignment routing and optimizing conflicting design rules have become bottlenecks in track assignment routing problems. This study addresses these bottlenecks by utilizing single-level horizontal and vertical Steiner trees to extract routability information of local wire nets, resolving the adaptation issue between global routing and detailed routing. The proposed algorithm enhances routability information by an average of 16.07% across ten benchmark circuits. Additionally, a Generative Neural Network model based on Conditional Variational Autoencoder (CVAE) is employed to improve the efficiency of track assignment routing, yielding significant simulation results. Furthermore, a negotiation-based tear-and-reassign approach is utilized to address track congestion issues, resulting in an average optimization of 26.03% in overlap cost, with a tradeoff of sacrificing 6.67% of wirelength on average

Delay Management Including Capacities of Stations

The question of delay management is whether passenger trains should wait for delayed feeder trains or should depart on time. Solutions to this problem strongly depend on the available capacity of the railway infrastructure. Although the limited capacity of the tracks has been considered in delay management models, the limited capacity of the stations has been neglected so far. In this paper, we develop a model for the delay management problem that includes the capacities of the stations. This model allows rescheduling the platform track assignment. Furthermore, we propose an iterative heuristic in which we first solve the delay management model with a fixed platform track assignment, and then improve this platform track assignment in each step. We show that the latter problem can be solved in polynomial time by describing it as a minimum cost flow model. Finally, we present an extension of the model that balances the delay of the passengers on one hand and the number of changes in the platform track assignment on the other. All models are evaluated on real-world instances from Netherlands Railways

Track Layouts of Graphs

A \emph{$(k,t)$-track layout} of a graph $G$ consists of a (proper) vertex $t$-colouring of $G$, a total order of each vertex colour class, and a (non-proper) edge $k$-colouring such that between each pair of colour classes no two monochromatic edges cross. This structure has recently arisen in the study of three-dimensional graph drawings. This paper presents the beginnings of a theory of track layouts. First we determine the maximum number of edges in a $(k,t)$-track layout, and show how to colour the edges given fixed linear orderings of the vertex colour classes. We then describe methods for the manipulation of track layouts. For example, we show how to decrease the number of edge colours in a track layout at the expense of increasing the number of tracks, and vice versa. We then study the relationship between track layouts and other models of graph layout, namely stack and queue layouts, and geometric thickness. One of our principle results is that the queue-number and track-number of a graph are tied, in the sense that one is bounded by a function of the other. As corollaries we prove that acyclic chromatic number is bounded by both queue-number and stack-number. Finally we consider track layouts of planar graphs. While it is an open problem whether planar graphs have bounded track-number, we prove bounds on the track-number of outerplanar graphs, and give the best known lower bound on the track-number of planar graphs.Comment: The paper is submitted for publication. Preliminary draft appeared as Technical Report TR-2003-07, School of Computer Science, Carleton University, Ottawa, Canad

Layout of Graphs with Bounded Tree-Width

A \emph{queue layout} of a graph consists of a total order of the vertices, and a partition of the edges into \emph{queues}, such that no two edges in the same queue are nested. The minimum number of queues in a queue layout of a graph is its \emph{queue-number}. A \emph{three-dimensional (straight-line grid) drawing} of a graph represents the vertices by points in $\mathbb{Z}^3$ and the edges by non-crossing line-segments. This paper contributes three main results: (1) It is proved that the minimum volume of a certain type of three-dimensional drawing of a graph $G$ is closely related to the queue-number of $G$. In particular, if $G$ is an $n$-vertex member of a proper minor-closed family of graphs (such as a planar graph), then $G$ has a $O(1)\times O(1)\times O(n)$ drawing if and only if $G$ has O(1) queue-number. (2) It is proved that queue-number is bounded by tree-width, thus resolving an open problem due to Ganley and Heath (2001), and disproving a conjecture of Pemmaraju (1992). This result provides renewed hope for the positive resolution of a number of open problems in the theory of queue layouts. (3) It is proved that graphs of bounded tree-width have three-dimensional drawings with O(n) volume. This is the most general family of graphs known to admit three-dimensional drawings with O(n) volume. The proofs depend upon our results regarding \emph{track layouts} and \emph{tree-partitions} of graphs, which may be of independent interest.Comment: This is a revised version of a journal paper submitted in October 2002. This paper incorporates the following conference papers: (1) Dujmovic', Morin & Wood. Path-width and three-dimensional straight-line grid drawings of graphs (GD'02), LNCS 2528:42-53, Springer, 2002. (2) Wood. Queue layouts, tree-width, and three-dimensional graph drawing (FSTTCS'02), LNCS 2556:348--359, Springer, 2002. (3) Dujmovic' & Wood. Tree-partitions of $k$-trees with applications in graph layout (WG '03), LNCS 2880:205-217, 200

Layout optimization in ultra deep submicron VLSI design

As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integration (VLSI) design. In this dissertation, we study several deep submicron problems (eg. coupling capacitance, antenna effect and delay variation) and propose optimization techniques to mitigate these DSM effects in the place-and-route stage of VLSI physical design. The place-and-route stage of physical design can be further divided into several steps: (1) Placement, (2) Global routing, (3) Layer assignment, (4) Track assignment, and (5) Detailed routing. Among them, layer/track assignment assigns major trunks of wire segments to specific layers/tracks in order to guide the underlying detailed router. In this dissertation, we have proposed techniques to handle coupling capacitance at the layer/track assignment stage, antenna effect at the layer assignment, and delay variation at the ECO (Engineering Change Order) placement stage, respectively. More specifically, at layer assignment, we have proposed an improved probabilistic model to quickly estimate the amount of coupling capacitance for timing optimization. Antenna effects are also handled at layer assignment through a linear-time tree partitioning algorithm. At the track assignment stage, timing is further optimized using a graph based technique. In addition, we have proposed a novel gate splitting methodology to reduce delay variation in the ECO placement considering spatial correlations. Experimental results on benchmark circuits showed the effectiveness of our approaches

On the Area of Hypercube Layouts

This paper precisely analyzes the wire density and required area in standard layout styles for the hypercube. The most natural, regular layout of a hypercube of N^2 nodes in the plane, in a N x N grid arrangement, uses floor(2N/3)+1 horizontal wiring tracks for each row of nodes. (The number of tracks per row can be reduced by 1 with a less regular design.) This paper also gives a simple formula for the wire density at any cut position and a full characterization of all places where the wire density is maximized (which does not occur at the bisection).Comment: 8 pages, 4 figures, LaTe