This paper precisely analyzes the wire density and required area in standard
layout styles for the hypercube. The most natural, regular layout of a
hypercube of N^2 nodes in the plane, in a N x N grid arrangement, uses
floor(2N/3)+1 horizontal wiring tracks for each row of nodes. (The number of
tracks per row can be reduced by 1 with a less regular design.) This paper also
gives a simple formula for the wire density at any cut position and a full
characterization of all places where the wire density is maximized (which does
not occur at the bisection).Comment: 8 pages, 4 figures, LaTe

Greenberg, Ronald I.

Guan, Lee

English

arXiv

This paper precisely analyzes the wire density and required area in standard styles for the hypercube. It shows that the most natural, regular layout of a hypercube of N^2 nodes in the plane, in a NxN grid arrangement, uses floor(2N/3)+1 horizontal wiring tracks for each row of nodes. (In the process, we see that the number of tracks per row can be reduced by 1 with a less regular design, as can also be seen from an independent argument of Bezrukov et al.) This paper also gives a simple formula for the wire density at any cut position and a full characterization of all places where the wire density is maximized (which does not occur at the bisection)

Name not available

On the Area of Hypercube Layouts

Loyola eCommons

Loyola University Chicago Loyola eCommons Computer Science: Faculty Publications and Other Works Faculty Publications 9-2002 On the Area of Hypercube Layouts Ronald I. Greenberg Rgreen@luc.edu Lee Guan Follow this and additional works at: https://ecommons.luc.edu/cs_facpubs  Part of the OS and Networks Commons, Theory and Algorithms Commons, and the VLSI and Circuits, Embedded and Hardware Systems Commons Author Manuscript This is a pre-publication author manuscript of the final, published article. Recommended Citation Ronald I. Greenberg and Lee Guan. On the area of hypercube layouts. Information Processing Letters, 84(1):41--46, September 2002. This Article is brought to you for free and open access by the Faculty Publications at Loyola eCommons. It has been accepted for inclusion in Computer Science: Faculty Publications and Other Works by an authorized administrator of Loyola eCommons. For more information, please contact ecommons@luc.edu. This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License. On the Area of Hypercube Layouts1Ronald I. GreenbergDept. of Mathematical and Computer Sciences, Loyola University, 6525 N.Sheridan Rd., Chicago, IL 60626-5385, USALee GuanAcecomm Corporation, 704 Quince Orchard Rd., Gaithersburg, MD 20878, USAAbstractThis paper precisely analyzes the wire density and required area in standard layoutstyles for the hypercube. It shows that the most natural, regular layout of a hy-percube of N2nodes in the plane, in a N N grid arrangement, uses b2N=3c+ 1horizontal wiring tracks for each row of nodes. (In the process, we see that thenumber of tracks per row can be reduced by 1 with a less regular design, as can alsobe seen from an independent argument of Bezrukov et al..) This paper also givesa simple formula for the wire density at any cut position and a full characteriza-tion of all places where the wire density is maximized (which does not occur at thebisection).Key words: interconnection networks, hypercube, wire density, VLSI layout area,mincut linear arrangement, optimal linear arrangement, channel routing1 IntroductionThe (binary) hypercube network has been widely considered as a networkfor parallel computing, but its VLSI layout requires a great deal of wiringarea. Studies of communications capabilities of the hypercube versus othernetworks (e.g., [1{5]) have varied the width of links between nodes in orderto equalize the hardware costs of the networks being compared under variouscost measures, some of which are closely related to VLSI layout area.Email address: lee guan@yahoo.com (Lee Guan).URL: http://www.cs.luc.edu/~rig (Ronald I. Greenberg).1Partially supported by NSF grant CCR-9321388.Preprint submitted to Elsevier Science 31 December 2001Recall that the interconnection pattern for a hypercube of N2nodes can bespecied by numbering the nodes from 0 to N2 1 and requiring a link betweenany two nodes whose numbers expressed in binary dier in exactly one bit.When the numbers dier in the ith bit from the right, we refer to the linkbetween the nodes as a dimension i link. (Though the links between nodesare generally considered to be bidirectional, we count them as one wire forsimplicity.Results quoted in this paper must be multiplied by 2 to obtain exactcorrespondence with results given in Dally [2] or Ranade and Johnsson [3].)The network cost measure used by Dally [2] is bisection width (the mini-mum number of wires that must be cut to divide the set of nodes into twoequal halves with no connections between them). This measure may be justi-ed by Thompson's lower bound [6,7] indicating that area is at least 1=4 ofthe square of the bisection width. Thompson's bound, however, does not givea precise correspondence between bisection width and area. Furthermore, asDally notes, the maximum wire density (number of wires that must cross acutline) does not occur at the bisection in the \normal layout" of the hyper-cube (nodes placed as in Figure 1). (Note that each row and column of thelayout is itself a hypercube, so we can focus henceforth on the layout of anN -node hypercube in a single row.)Ranade and Johnsson [3] consider the actual area required for the normallayout by bounding the number of horizontal tracks per row required to lay outthe interconnections (following the common approach of placing vertical wiresin one chip layer and horizontal wires in another). (The situation involvingvertical tracks is completely analogous to that involving horizontal tracks.)They focus, however, on optimality to within an unspecied constant factorand only upper bound the number of tracks per row as N   1, as obtained bythe assignment of wires to tracks illustrated in Figure 1.A more sophisticated track assignment by Chen, Agrawal, and Burke [8] (witha dierent ordering of the nodes), yields N   lgN tracks per row.2A still better measure for the number of tracks per row, utilized in [4,5], isb2N=3c. That this number represents the congestion for the natural embeddingof the hypercube into a square grid also follows from an independent statementof Nakano [9] and an argument of Bezrukov et al. [10].This paper gives a short alternative proof of the congestion result that alsoyields a concise formula for the wire density at every cut position and a fullcharacterization of all positions where density is maximized. The analysis isthen extended to account for the exact placement of the terminals and wires inthe layout. It would be desirable to make all nodes identical, e.g., by placingthe connections of each node in order of dimension (as in Figure 1); this2We use lg x for log2x, and we assume N is a power of 2.2.0 1 2 3 4 5 6 78 9 10 11 12 13 14 1516 17 18 19 20 21 22 2324 25 26 27 28 29 30 3132 33 34 35 36 37 38 3940 41 42 43 44 45 46 4748 49 50 51 52 53 54 5556 57 58 59 60 61 62 63Fig. 1. The normal hypercube layout and a naive track assignment for N2= 64.would be particularly convenient when implementing the common form ofhypercube algorithm referred to as a \normal algorithm" (e.g., see [11]), inwhich only one dimension of communication links is used at any step, andthe dimensions are used consecutively. Uniformity of nodes is also helpful forassembling the system and for replacing defective nodes. We show that sucha uniform approach incurs a penalty of exactly one track per row in the VLSIlayout, whereas full freedom to permute the terminals allows a layout withb2N=3c tracks per row.The rest of this paper is organized as follows. Section 2 introduces notation andprovides background regarding the congestion result. Section 3, gives a simpleformula for the wire density at each intercolumn position and a full character-ization of those positions where the density is maximized. Then the analysisis extended to include the density at cutlines that run through nodes, whichcompletes the analysis of the number of wiring tracks required. Section 4, com-ments on hypercube layouts in which the nodes are placed dierently than inthe normal scheme illustrated in Figure 1.2 BackgroundAs a rst step towards determining the usage of wiring tracks in the nor-mal hypercube layout, we focus on the intercolumn wire density per row. Wesketch here a short proof, shown fully in [12], that the maximum intercol-umn wire density per row in the normal hypercube layout is b2N=3c and thatthe leftmost intercolumn position where this maximum is realized is position3b(N + 1)=3c. In the process we introduce notation for our main results in thenext section and note important symmetry properties.We dene f(i; k) to be the number of dimension k links (i.e., links spanning2k 1columns) that cross intercolumn position i in the normal layout. Using0 to denote the position to the left of all the nodes, it is easy to see thatthe pattern for f(0; k), f(1; k), . . . , f(N   1; k) is 0, 1, 2, . . . , 2k 1  1, 2k 1,2k 1  1, 2k 1  2, . . . , 1, and repeat as necessary; we may express this asf(i; k) = i1  2i  12k 1mod 2mod 2k: (1)Then we dene S(i;N) to be the total number of connections crossing inter-column position i in the normal layout, i.e.,S(i;N) =lgNXk=1f(i; k) : (2)For the proof sketch in this section, there is also a more convenient mathe-matical expression for the maximum intercolumn wire density and and theleftmost position where the maximum is realized:m(N)= (4N   ( 1)lgN  3)=6 (3)p(N) = (N   ( 1)lgN)=3 (4)Then the result discussed in this section is that max0<i<NS(i;N) = m(N)and that i = p(N) is the least i at which the maximum is achieved. The resultfollows from the following Lemma and two Theorems:Lemma 1 S(i;N) = S(N   i;N) for 0 < i < N .Proof sketch The result follows from showing f(i; k) = f(N   i; k) for 0 <i < N and 1  k  lgN , which follows from Equation 1.Theorem 2 S(p(N); N) = m(N).Proof sketch The proof is by induction on lgN using Equations 1{4 andLemma 1. 2Now we need only that S(i;N)  m(N), but the following theorem includesadditional information to make the proof easier:4.0 1 2 3 4 5 6 7Fig. 2. Wiring a row in m(N) = 5 tracks for N = 8..0 1 2 3 4 5 6 7Fig. 3. Wiring a row requires m(N)+1 = 6 tracks for N = 8 when the wires leavingeach node are in order of increasing dimension.Theorem 3 S(i;N)  minfm(N);m(N)  (p(N)  i)g for 0 < i < N .Proof sketch We again use induction on lgN .We rst use Equations 1{4 to show that S(i;N)  m(N)  (p(N)  i). Thenwe show S(i;N)  m(N) by considering the three cases of i > N=2, i  p(N),and p(N) < i  N=2 and using Lemma 1 again. 23 Number of wiring tracksThough we know the maximum intercolumn wire density per row in the layoutof Figure 1, we still need to determine the number of horizontal wiring tracksrequired to route the wires. Fortunately, an early channel routing algorithmof Hashimoto and Stevens [13], the left-edge algorithm, guarantees that thedensity and number of tracks are equal, since we have no vertical constraints(e.g., see [14]). To obtain a layout using exactly m(N) tracks, however, wemust be free to permute the locations of connections on each hypercube nodeso that the density (maximum number of wires crossing a vertical line) is nohigher when the cutline runs through nodes than when it runs between nodes.A layout using m(N) = 5 tracks for one row of the 64-node hypercube isillustrated in Figure 2. (This gure uses a track assignment slightly dierentthan the assignment produced by the left edge algorithm in order to reducethe number of wire crossings.)If we require that each node has its connections in order of dimensions 1, 2,. . . lgN , we cannot achieve a routing in m(N) tracks when N > 2; Figure 3with 6 tracks shows the best layout of a row when N = 8. Even with thisxed order of connections, however, the density (and therefore the number oftracks) is just m(N) + 1 for N > 2. Our approach to obtaining this strongerresult also produces a characterization of all locations where the density ismaximized. We encapsulate these results in the following two Theorems.5Theorem 4 The values of i in binary for which S(i;N) is maximized arethose obtained as follows. Starting from the leftmost bit of i and moving right,choose pairs of bits to be 01 or 10 except that when lgN is even, the last pairmay be 11. When lgN is odd, the 1 remaining bit is set to 1.PROOF. Considering the number i represented in binary, dene b(i; j) to bethe bit in the j-th position from the right (1  j  lgN), and dene e(i; j) tobe the excess of 1's over 0's in bit positions greater than j (i.e., the number of1's minus the number of 0's in the relevant portion of i's representation). Also,let r denote the number of consecutive 0's at the right end of i's representation.(Using the notation 0rto represent a string of r 0's, note that with i of theform X10r, i 1 is X01r, and  i is X10r, where X is the bitwise complementofX.) Starting from the denitions of S(i;N) and f(i; k) in Equations 2 and 1,we can express S(i;N) aslgNXk=1i(1  2b(i  1; k)) mod 2k=lgNXk=1kXj=1b(i(1  2b(i  1; k)); j)  2j 1=lgNXj=1lgNXk=j2j 18><>:b(i; j) if b(i  1; k) = 0b( i; j) if b(i  1; k) = 1=lgNXj=12j 1b( i; j)+ b(i; j)2(lgN   j + 1) +b( i; j)  b(i; j)2e(i  1; j   1)=rXj=10 + 2r(lgN   r) +lgNXj=r+22j 2[lgN   j + 1+ (1  2b(i; j))e(i  1; j   1)]= 2r(lgN   r) + lgNlgNXj=r+22j 2 lgNXj=r+2j2j 2+lgNXj=r+22j 2(1  2b(i; j))e(i; j)=12N +lgNXj=r+22j 2(1  2b(i; j))e(i; j)=12N  r+1Xj=12j 2(1  2b(i; j))e(i; j)+lgNXj=12j 2(1  2b(i; j))e(i; j)=12N  rXj=12j 2(e(i; 0)+ j) + 2r 1(e(i; 0)+ r   1) +lgNXj=12j 2(1  2b(i; j))e(i; j)=12(e(i; 0)+N   1) +lgN 1Xj=12j 28><>:e(i; j) if b(i; j) = 0 e(i; j) if b(i; j) = 1: (5)From this expression, we can see that S(i;N) is maximized by setting pairs of6bits greedily from the left end of i's representation, except for a slight variationwhen j becomes small, as in the theorem statement. (It is also easy to checkthat this maximum equals m(N) of Equation 3.) 2Now we proceed to analyze the maximum density in a row of the layout whenit is required that each node has its connections in order of dimensions 1, 2,. . . lgN . We dene T (i; p;N) to be the number of wires crossing a cutlinejust to the right of the p-th terminal position on a node in column i   1 for1  p  lgN (so T (i; lgN;N) = S(i;N)).Theorem 5 For N > 2, the maximum value of T (i; p;N) over all i and p ism(N) + 1 and is realized at an i for which S(i;N) = m(N).PROOF. We can express T (i; p;N) in terms of S(i;N) by using the notationdened at the beginning of the proof of Theorem 4; specically, T (i; p;N) =S(i;N)+ e(i  1; p). The term e(i  1; p) can be reexpressed in terms of e(i; p)based on the value of r dened above. For p > r, we have e(i  1; p) = e(i; p).For p  r, we have e(i  1; p) = e(i; p) + 2(r   p   1).When r = 0, we know p > r, and we see that the strategy for choosingi described in Theorem 4 remains optimal, since the e(i; p) term is smallcompared to 2jfor most values of j in Equation 5. With such an i, the largeste(i; p) we can achieve is 1 (if at least one of the pairs of bits under the strategyof Theorem 4 is 10 or 11).When r = 1, the situation is essentially the same as for r = 0, except thatwe must choose p > 1 to maximize e(i  1; p). We still must choose an i thatmaximizes S(i;N), and e(i  1; p) will be at most 1.Choosing r  2 contradicts choosing i to maximize S(i;N), and the decitin the value of S(i;N) cannot be recouped through the term e(i  1; p). (Forr = 2, e(i   1; p) cannot exceed e(i; p), while increasing values of r causeincreasing deterioration in the value of S(i;N).) 2Note that this result is not an idiosyncrasy of the particular ordering chosen forthe terminals on each node. Rather, because of the symmetry in the layout, itis apparent than any ordering that is the same for all nodes leads to m(N)+1tracks; an ordering that reduces T (i; p;N) where it exceeds m(N) will makea corresponding increase from m(N) to m(N) + 1 in another position.7.0 1 3 2 6 7 5 4Fig. 4. The top row of a gray code derived layout for N = 8.4 Alternative layoutsAnother frequently considered method of mapping hypercube nodes to a reg-ular grid is to use a gray code derived layout. The numbering of nodes inthe top row of a gray code layout for a 64-node hypercube is illustrated inFigure 4. (Here we have not required the terminals on each node to be in di-mension order.) Ranade and Johnsson [3] noted that the area and maximumwire length for the normal layout and the gray code layout are the same up toa constant factor. In fact, the arguments of Sections 2 and 3 can be extendedto show that the maximumwire density and number of wiring tracks requiredper row is exactly the same for the gray code layout as for the normal layout,including a one track penalty when the nodes are identical. It is also easy toshow that the total (horizontal) wire length per row is the same (in terms ofthe number of columns spanned). The maximum (horizontal) wire length in arow of the normal layout, however, is essentially half as large as for the graycode layout.The results of Harper [15,16], Nakano [9], and Bezrukov et al. [10] show thatthe normal layout minimizes total wire length and intercolumn wire density,while a dierent layout minimizes maximum wire length. Bezrukov et al. alsoconsider two new cost measures for embeddings of hypercubes into grids basedon the frequent use of normal algorithms [17].References[1] S. Abraham, K. Padmanabhan, Performance of multicomputer networks underpin-out constraints, Journal of Parallel and Distributed Computing (1991) 237{248.[2] W. J. Dally, Performance analysis of k-ary n-cube interconnection networks,IEEE Trans. Computers 39 (6) (1990) 775{785.[3] A. G. Ranade, S. L. Johnsson, The communication eciency of meshes, booleancubes and cube connected cycles for wafer scale integration, in: Proceedings ofthe 1987 International Conference on Parallel Processing, 1987, pp. 479{482.[4] R. I. Greenberg, L. Guan, An empirical comparison of area-universal and otherparallel computing networks, in: Proceedings of the ISCA 9th InternationalConference on Parallel and Distributed Computing Systems, 1996, pp. 260{267.8[5] R. I. Greenberg, L. Guan, An empirical comparison of networks and routingstrategies for parallel computation, in: Proceedings of the Eighth IASTEDInternational Conference Parallel and Distributed Computing and Systems,Chicago, 1996, pp. 265{269.[6] C. D. Thompson, Area-time complexity for VLSI, in: Proceedings of the 11thACM Symposium on Theory of Computing, ACM Press, 1979, pp. 81{88.[7] C. D. Thompson, A complexity theory for VLSI, Ph.D. thesis, Department ofComputer Science, Carnegie-Mellon University (1980).[8] C. Chen, D. P. Agrawal, J. R. Burke, dBCube: A new class of hierarchicalmultiprocessor interconnection networks with area ecient layout, IEEE Trans.Parallel and Distributed Systems 4 (12) (1993) 1332{1344.[9] K. Nakano, Linear layouts of generalized hypercubes, in: Proceedings of the 19thInternational Workshop on Graph-Theoretic Concepts in Computer Science(WG '93), Springer-Verlag, 1994, pp. 364{365.[10] S. L. Bezrukov, J. D. Chavez, L. H. Harper, M. Rottger, U.-P. Schroeder, Thecongestion of n-cube layout on a rectangular grid, Discrete Mathematics 213(2000) 13{19.[11] F. T. Leighton, Introduction to Parallel Algorithms and Architectures: Arrays Trees  Hypercubes, Morgan Kaufmann, 1992.[12] R. I. Greenberg, L. Guan, On the area of hypercube layouts, Eprint cs-dc/0105034, Comp. Sci. Res. Repository, http://arXiv.org/abs/cs.DC/0105034(2001).[13] A. Hashimoto, J. Stevens, Wire routing by optimizing channel assignmentwithin large apertures, in: Proceedings of the 8th ACM/IEEE DesignAutomation Conference, IEEE Computer Society Press, 1971, pp. 155{169.[14] T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout, JohnWiley, 1990.[15] L. H. Harper, Optimal assignments of numbers to vertices, Journal of theSociety for Industrial and Applied Mathematics 12 (1) (1964) 131{135.[16] L. H. Harper, Optimal numberings and isoperimetric problems on graphs,Journal of Combinatorial Theory 1 (1966) 385{393.[17] S. L. Bezrukov, J. D. Chavez, L. H. Harper, M. Rottger, U.-P. Schroeder,Embedding of hypercubes into grids, in: MFCS '98, Springer-Verlag, 1998, pp.693{701, lecture Notes in Computer Science 1450.9

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On the Area of Hypercube Layouts

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