11,145 research outputs found
A Library-Based Synthesis Methodology for Reversible Logic
In this paper, a library-based synthesis methodology for reversible circuits
is proposed where a reversible specification is considered as a permutation
comprising a set of cycles. To this end, a pre-synthesis optimization step is
introduced to construct a reversible specification from an irreversible
function. In addition, a cycle-based representation model is presented to be
used as an intermediate format in the proposed synthesis methodology. The
selected intermediate format serves as a focal point for all potential
representation models. In order to synthesize a given function, a library
containing seven building blocks is used where each building block is a cycle
of length less than 6. To synthesize large cycles, we also propose a
decomposition algorithm which produces all possible minimal and inequivalent
factorizations for a given cycle of length greater than 5. All decompositions
contain the maximum number of disjoint cycles. The generated decompositions are
used in conjunction with a novel cycle assignment algorithm which is proposed
based on the graph matching problem to select the best possible cycle pairs.
Then, each pair is synthesized by using the available components of the
library. The decomposition algorithm together with the cycle assignment method
are considered as a binding method which selects a building block from the
library for each cycle. Finally, a post-synthesis optimization step is
introduced to optimize the synthesis results in terms of different costs.Comment: 24 pages, 8 figures, Microelectronics Journal, Elsevie
Synthesis and Optimization of Reversible Circuits - A Survey
Reversible logic circuits have been historically motivated by theoretical
research in low-power electronics as well as practical improvement of
bit-manipulation transforms in cryptography and computer graphics. Recently,
reversible circuits have attracted interest as components of quantum
algorithms, as well as in photonic and nano-computing technologies where some
switching devices offer no signal gain. Research in generating reversible logic
distinguishes between circuit synthesis, post-synthesis optimization, and
technology mapping. In this survey, we review algorithmic paradigms ---
search-based, cycle-based, transformation-based, and BDD-based --- as well as
specific algorithms for reversible synthesis, both exact and heuristic. We
conclude the survey by outlining key open challenges in synthesis of reversible
and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table
Generating reversible circuits from higher-order functional programs
Boolean reversible circuits are boolean circuits made of reversible
elementary gates. Despite their constrained form, they can simulate any boolean
function. The synthesis and validation of a reversible circuit simulating a
given function is a difficult problem. In 1973, Bennett proposed to generate
reversible circuits from traces of execution of Turing machines. In this paper,
we propose a novel presentation of this approach, adapted to higher-order
programs. Starting with a PCF-like language, we use a monadic representation of
the trace of execution to turn a regular boolean program into a
circuit-generating code. We show that a circuit traced out of a program
computes the same boolean function as the original program. This technique has
been successfully applied to generate large oracles with the quantum
programming language Quipper.Comment: 21 pages. A shorter preprint has been accepted for publication in the
Proceedings of Reversible Computation 2016. The final publication is
available at http://link.springer.co
A Cost- Effective Design of Reversible Programmable Logic Array
In the recent era, Reversible computing is a growing field having
applications in nanotechnology, optical information processing, quantum
networks etc. In this paper, the authors show the design of a cost effective
reversible programmable logic array using VHDL. It is simulated on xilinx ISE
8.2i and results are shown. The proposed reversible Programming logic array
called RPLA is designed by MUX gate [10] & Feynman gate for 3- inputs, which is
able to perform any reversible 3- input logic function or Boolean function.
Furthermore the quantized analysis with camparitive finding is shown for the
realized RPLA against the existing one. The result shows improvement in the
quantum cost and total logical caculation in proposed RPLA.Comment: 6 Pages, 9 Figure
Polynomial-time T-depth Optimization of Clifford+T circuits via Matroid Partitioning
Most work in quantum circuit optimization has been performed in isolation
from the results of quantum fault-tolerance. Here we present a polynomial-time
algorithm for optimizing quantum circuits that takes the actual implementation
of fault-tolerant logical gates into consideration. Our algorithm
re-synthesizes quantum circuits composed of Clifford group and T gates, the
latter being typically the most costly gate in fault-tolerant models, e.g.,
those based on the Steane or surface codes, with the purpose of minimizing both
T-count and T-depth. A major feature of the algorithm is the ability to
re-synthesize circuits with additional ancillae to reduce T-depth at
effectively no cost. The tested benchmarks show up to 65.7% reduction in
T-count and up to 87.6% reduction in T-depth without ancillae, or 99.7%
reduction in T-depth using ancillae.Comment: Version 2 contains substantial improvements and extensions to the
previous version. We describe a new, more robust algorithm and achieve
significantly improved experimental result
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