Energy-efficient Wireless Analog Sensing for Persistent Underwater Environmental Monitoring

The design of sensors or "things" as part of the new Internet of Underwater Things (IoUTs) paradigm comes with multiple challenges including limited battery capacity, not polluting the water body, and the ability to track continuously phenomena with high temporal/spatial variability. We claim that traditional digital sensors are incapable to meet these demands because of their high power consumption, high complexity (cost), and the use of non-biodegradable materials. To address the above challenges, we propose a novel architecture consisting of a sensing substrate of dense analog biodegradable sensors over which lies the traditional Wireless Sensor Network (WSN). The substrate analog biodegradable sensors perform Shannon mapping (a data-compression technique) using just a single Field Effect Transistor (FET) without the need for power-hungry Analog-to-Digital Converters (ADCs) resulting in much lower power consumption, complexity, and the ability to be powered using only sustainable energy-harvesting techniques. A novel and efficient decoding technique is also presented. Both encoding/decoding techniques have been verified via Spice and MATLAB simulations accounting for underwater acoustic channel variations.Comment: 5 pages, IEEE UComms 201

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Analog Spiking Neuromorphic Circuits and Systems for Brain- and Nanotechnology-Inspired Cognitive Computing

Human society is now facing grand challenges to satisfy the growing demand for computing power, at the same time, sustain energy consumption. By the end of CMOS technology scaling, innovations are required to tackle the challenges in a radically different way. Inspired by the emerging understanding of the computing occurring in a brain and nanotechnology-enabled biological plausible synaptic plasticity, neuromorphic computing architectures are being investigated. Such a neuromorphic chip that combines CMOS analog spiking neurons and nanoscale resistive random-access memory (RRAM) using as electronics synapses can provide massive neural network parallelism, high density and online learning capability, and hence, paves the path towards a promising solution to future energy-efficient real-time computing systems. However, existing silicon neuron approaches are designed to faithfully reproduce biological neuron dynamics, and hence they are incompatible with the RRAM synapses, or require extensive peripheral circuitry to modulate a synapse, and are thus deficient in learning capability. As a result, they eliminate most of the density advantages gained by the adoption of nanoscale devices, and fail to realize a functional computing system. This dissertation describes novel hardware architectures and neuron circuit designs that synergistically assemble the fundamental and significant elements for brain-inspired computing. Versatile CMOS spiking neurons that combine integrate-and-fire, passive dense RRAM synapses drive capability, dynamic biasing for adaptive power consumption, in situ spike-timing dependent plasticity (STDP) and competitive learning in compact integrated circuit modules are presented. Real-world pattern learning and recognition tasks using the proposed architecture were demonstrated with circuit-level simulations. A test chip was implemented and fabricated to verify the proposed CMOS neuron and hardware architecture, and the subsequent chip measurement results successfully proved the idea. The work described in this dissertation realizes a key building block for large-scale integration of spiking neural network hardware, and then, serves as a step-stone for the building of next-generation energy-efficient brain-inspired cognitive computing systems

Neuro-inspired electronic skin for robots

Touch is a complex sensing modality owing to large number of receptors (mechano, thermal, pain) nonuniformly embedded in the soft skin all over the body. These receptors can gather and encode the large tactile data, allowing us to feel and perceive the real world. This efficient somatosensation far outperforms the touch-sensing capability of most of the state-of-the-art robots today and suggests the need for neural-like hardware for electronic skin (e-skin). This could be attained through either innovative schemes for developing distributed electronics or repurposing the neuromorphic circuits developed for other sensory modalities such as vision and audio. This Review highlights the hardware implementations of various computational building blocks for e-skin and the ways they can be integrated to potentially realize human skin–like or peripheral nervous system–like functionalities. The neural-like sensing and data processing are discussed along with various algorithms and hardware architectures. The integration of ultrathin neuromorphic chips for local computation and the printed electronics on soft substrate used for the development of e-skin over large areas are expected to advance robotic interaction as well as open new avenues for research in medical instrumentation, wearables, electronics, and neuroprosthetics

Analog VLSI Circuits for Biosensors, Neural Signal Processing and Prosthetics

Stroke, spinal cord injury and neurodegenerative diseases such as ALS and Parkinson's debilitate their victims by suffocating, cleaving communication between, and/or poisoning entire populations of geographically correlated neurons. Although the damage associated with such injury or disease is typically irreversible, recent advances in implantable neural prosthetic devices offer hope for the restoration of lost sensory, cognitive and motor functions by remapping those functions onto healthy cortical regions. The research presented in this thesis is directed toward developing enabling technology for totally implantable neural prosthetics that could one day restore lost sensory, cognitive and motor function to the victims of debilitating neural injury or disease. There are three principal components to this work. First, novel integrated biosensors have been designed and implemented to transduce weak extra-cellular electrical potentials and optical signals from cells cultured directly on the surface of the sensor chips, as well as to manipulate cells on the surface of these chips. Second, a method of detecting and identifying stereotyped neural signals, or action potentials, has been mapped into silicon circuits which operate at very low power levels suitable for implantation. Third, as one small step towards the development of cognitive neural implants, a learning silicon synapse has been implemented and a neural network application demonstrated. The original contributions of this dissertation include: * A contact image sensor that adapts to background light intensity and can asynchronously detect statistically significant optical events in real-time; * Programmable electrode arrays for enhanced electrophysiological recording, for directing cellular growth, for site-specific in situ bio-functionalization, and for analyte and particulate collection; * Ultra-low power, programmable floating gate template matching circuits for the detection and classification of neural action potentials; * A two transistor synapse that exhibits spike timing dependent plasticity and can implement adaptive pattern classification and silicon learning

Journal of Telecommunications and Information Technology, 2004, nr 1

kwartalni

Second year technical report on-board processing for future satellite communications systems

Advanced baseband and microwave switching techniques for large domestic communications satellites operating in the 30/20 GHz frequency bands are discussed. The nominal baseband processor throughput is one million packets per second (1.6 Gb/s) from one thousand T1 carrier rate customer premises terminals. A frequency reuse factor of sixteen is assumed by using 16 spot antenna beams with the same 100 MHz bandwidth per beam and a modulation with a one b/s per Hz bandwidth efficiency. Eight of the beams are fixed on major metropolitan areas and eight are scanning beams which periodically cover the remainder of the U.S. under dynamic control. User signals are regenerated (demodulated/remodulated) and message packages are reformatted on board. Frequency division multiple access and time division multiplex are employed on the uplinks and downlinks, respectively, for terminals within the coverage area and dwell interval of a scanning beam. Link establishment and packet routing protocols are defined. Also described is a detailed design of a separate 100 x 100 microwave switch capable of handling nonregenerated signals occupying the remaining 2.4 GHz bandwidth with 60 dB of isolation, at an estimated weight and power consumption of approximately 400 kg and 100 W, respectively