Design and analysis of efficient QCA reversible adders

Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS technology. In a QCA structure, information destruction plays an essential role in the overall heat dissipation, and in turn in the power consumption of the system. Therefore, reversible logic, which significantly controls the information flow of the system, is deemed suitable to achieve ultra-low-power structures. In order to benefit from the opportunities QCA and reversible logic provide, in this paper, we first review and implement prior reversible full-adder art in QCA. We then propose a novel reversible design based on three- and five-input majority gates, and a robust one-layer crossover scheme. The new full-adder significantly advances previous designs in terms of the optimization metrics, namely cell count, area, and delay. The proposed efficient full-adder is then used to design reversible ripple-carry adders (RCAs) with different sizes (i.e., 4, 8, and 16 bits). It is demonstrated that the new RCAs lead to 33% less garbage outputs, which can be essential in terms of lowering power consumption. This along with the achieved improvements in area, complexity, and delay introduces an ultra-efficient reversible QCA adder that can be beneficial in developing future computer arithmetic circuits and architecture

Quantum-dot Cellular Automata: Review Paper

Quantum-dot Cellular Automata (QCA) is one of the most important discoveries that will be the successful alternative for CMOS technology in the near future. An important feature of this technique, which has attracted the attention of many researchers, is that it is characterized by its low energy consumption, high speed and small size compared with CMOS.  Inverter and majority gate are the basic building blocks for QCA circuits where it can design the most logical circuit using these gates with help of QCA wire. Due to the lack of availability of review papers, this paper will be a destination for many people who are interested in the QCA field and to know how it works and why it had taken lots of attention recentl

IMPLEMENTATION OF QCA COMPARATOR ARCHITECTURE FOR POWER CRITICAL APPLICATIONS

Quantum-dot cellular automata (QCA) are an attractive emerging technology suitable for the development of ultra-dense-low-power high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators. Nevertheless, since the design of digital circuits in QCA still poses several challenges, novel implementation strategies and methodologies are highly desirable. This paper proposes a new design approach oriented to the implementation of binary comparators in QCA. New formulations of basic logic equations required to perform the comparison function are proposed. The new strategy has been exploited in the design of two different comparator architectures and for several operands word lengths. With respect to existing counterparts, the comparators proposed here exhibit significantly higher speed and reduced overall area. The proposed scheme, we deal with 32-bit numbers with less number of resources unlike conventional comparators, which leads to the realization of low power and area efficient comparator. This comparator can be widely used in central processing units (CPUs) and microcontrollers

IMPLEMENTATION OF AREA AND DELAY COMPARISON 0.FUNCTION USING QUANTUM-DOT CELLULAR AUTOMATA

Quantum-dot cellular automata (QCA) are an attractive emerging technology suitable for the development of ultra-dense-low-power high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators. Nevertheless, sincethe design of digital circuits in QCA still poses several challenges, novel implementation strategies and methodologies are highly desirable. This paper proposes a new design approach oriented to the implementation of binary comparators in QCA. New formulations of basic logic equations required to perform the comparison function are proposed. The new strategy has been exploited in the design of two different comparator architectures and for several operands word lengths. With respect to existing counterparts, the comparators proposed here exhibit significantly higher speed and reduced overall area. The proposed scheme, we deal with 32-bit numbers with less number of resources unlike conventional comparators, which leads to the realization of low power and area efficient comparator. This comparator can be widely used in central processing units (CPUs) and microcontrollers

AN OPTIMIZED AREA AND DELAY PARALLEL PREFIX TREE METHODOLOGY FOR QUANTUM-DOT CELLULAR AUTOMATA

Quantum-dot cellular automata (QCA) are a conspicuous technology suitable for the development of ultra-dense-low-power high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators. In this paper area and power optimized QCA comparator is presented for developing a 32bit full comparator. It is able to achieve lower area and power consumption. With respect to existing counterparts the comparators proposed here exhibit significantly higher speed and reduced overall area and power. The structures proposed in provide higher computational capabilities, and circuits able to separately recognize all the three possible conditions i.e., a = b, a > b, and a < b. The new strategy has been exploited in the design of two different comparator architectures and for several operands word lengths. The proposed scheme, we deal with 32-bit numbers with less number of resources unlike conventional comparators, which leads to the realization of low power and area efficient comparator. This comparator can be widely used in central processing units (CPUs) and microcontrollers

VLSI IMPLEMENTATION OF AREA AND POWER OPTIMIZED QUANTUM DOT CELLULAR AUTOMATA COMPARATOR

Quantum-dot cellular automata (QCA) are a conspicuous technology suitable for the development of ultra-dense-low-power high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators. In this paper area and power optimized QCA comparator is presented for developing a 32bit full comparator. It is able to achieve lower area and power consumption. With respect to existing counterparts the comparators proposed here exhibit significantly higher speed and reduced overall area and power. The structures proposed in provide higher computational capabilities, and circuits able to separately recognize all the three possible conditions i.e., a = b, a > b, and a < b. The new strategy has been exploited in the design of two different comparator architectures and for several operands word lengths. The proposed scheme, we deal with 32-bit numbers with less number of resources unlike conventional comparators, which leads to the realization of low power and area efficient comparator

Data tag control for quantum-dot cellular automata

The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data tag using the local tag decoder, communicating the instructions to a processing element, communicating the data along a second wire-like element to the processing element, and processing the data with the processing element according to the instructions. A length of the first wire-like elements and a length of the second wire-like element are approximately the same such that communication of the instructions and the data to the processing element are synchronized.Board of Regents, University of Texas Syste

Multiple bit error correcting architectures over finite fields

This thesis proposes techniques to mitigate multiple bit errors in GF arithmetic circuits. As GF arithmetic circuits such as multipliers constitute the complex and important functional unit of a crypto-processor, making them fault tolerant will improve the reliability of circuits that are employed in safety applications and the errors may cause catastrophe if not mitigated. Firstly, a thorough literature review has been carried out. The merits of efficient schemes are carefully analyzed to study the space for improvement in error correction, area and power consumption. Proposed error correction schemes include bit parallel ones using optimized BCH codes that are useful in applications where power and area are not prime concerns. The scheme is also extended to dynamically correcting scheme to reduce decoder delay. Other method that suits low power and area applications such as RFIDs and smart cards using cross parity codes is also proposed. The experimental evaluation shows that the proposed techniques can mitigate single and multiple bit errors with wider error coverage compared to existing methods with lesser area and power consumption. The proposed scheme is used to mask the errors appearing at the output of the circuit irrespective of their cause. This thesis also investigates the error mitigation schemes in emerging technologies (QCA, CNTFET) to compare area, power and delay with existing CMOS equivalent. Though the proposed novel multiple error correcting techniques can not ensure 100% error mitigation, inclusion of these techniques to actual design can improve the reliability of the circuits or increase the difficulty in hacking crypto-devices. Proposed schemes can also be extended to non GF digital circuits

Nanosensor Data Processor in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is an attractive nanotechnology with the potential alterative to CMOS technology. QCA provides an interesting paradigm for faster speed, smaller size, and lower power consumption in comparison to transistor-based technology, in both communication and computation. This paper describes the design of a 4-bit multifunction nanosensor data processor (NSDP). The functions of NSDP contain (i) sending the preprocessed raw data to high-level processor, (ii) counting the number of the active majority gates, and (iii) generating the approximate sigmoid function. The whole system is designed and simulated with several different input data

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within