Timing Anomalies Reloaded

Computing tight WCET bounds in the presence of timing anomalies - found in almost any modern hardware architecture - is a major challenge of timing analysis. In this paper, we renew the discussion about timing anomalies, demonstrating that even simple hardware architectures are prone to timing anomalies. We furthermore complete the list of timing-anomalous cache replacement policies, proving that the most-recently-used replacement policy (MRU) also exhibits a domino effect

Tracking and data system support for the Mariner Mars 1971 mission. Volume 2: First trajectory correction maneuver through orbit insertion

The Deep Space Tracking and Data System activities in support of the Mariner Mars 1971 project from the first trajectory correction maneuver on 4 June 1971 through cruise and orbit insertion on 14 November 1971 are presented. Changes and updates to the TDS requirements and to the plan and configuration plus detailed information on the TDS flight support performance evaluation and the preorbital testing and training are included. With the loss of Mariner 8 at launch, a few changes to the Mariner Mars 1971 requirements, plan, and configuration were necessitated. Mariner 9 is now assuming the former mission plan of Mariner 8, including the TV mapping cycles and a 12-hr orbital period. A second trajectory correction maneuver was not required because of the accuracy of the first maneuver. All testing and training for orbital operations were completed satisfactorily and on schedule. The orbit insertion was accomplished with excellent results

Formal Executable Models for Automatic Detection of Timing Anomalies

A timing anomaly is a counterintuitive timing behavior in the sense that a local fast execution slows down an overall global execution. The presence of such behaviors is inconvenient for the WCET analysis which requires, via abstractions, a certain monotony property to compute safe bounds. In this paper we explore how to systematically execute a previously proposed formal definition of timing anomalies. We ground our work on formal designs of architecture models upon which we employ guided model checking techniques. Our goal is towards the automatic detection of timing anomalies in given computer architecture designs

Tracking and data system support for Surveyor mission 5, volume 3

Surveyor 5 tracking and data system activities evaluated from planning to final flight stage

Detecting Selected Network Covert Channels Using Machine Learning

International audienceNetwork covert channels break a computer's security policy to establish a stealthy communication. They are a threat being increasingly used by malicious software. Most previous studies on detecting network covert channels using Machine Learning (ML) were tested with a dataset that was created using one single covert channel tool and also are ineffective at classifying covert channels into patterns. In this paper, selected ML methods are applied to detect popular network covert channels. The capacity of detecting and classifying covert channels with high precision is demonstrated. A dataset was created from nine standard covert channel tools and the covert channels are then accordingly classified into patterns and labelled. Half of the generated dataset is used to train three different ML algorithms. The remaining half is used to verify the algorithms' performance. The tested ML algorithms are Support Vector Machines (SVM), k-Nearest Neighbors (k-NN) and Deep Neural Networks (DNN). The k-NN model demonstrated the highest precision rate at 98% detection of a given covert channel and with a low false positive rate of 1%

Creating Public Transport Networks for Strategic Transport Modelling from Electronic Timetable Data

Public transport networks are one of the key inputs for multi-modal strategic transport models. Traditionally these networks were created manually, nowadays there is electronic timetable data available. Theoretically it should be easy to reformat the data and import into the model. In practice a number of complications arise including selecting services for modelled time periods, what degree of stopping pattern variation and routing variation can be validly combined before a different service is coded. There are also differences between modes, both in data detail and the processes required to effectively represent services. Another issue to consider is the allocation of bus stops to existing network nodes, or when new network nodes should be added.It is desirable that the process can be automated so that new timetable information can be readily incorporated. This paper describes the processes that the NSW Bureau of Transport Statistics (BTS) (formerly Transport Data Centre) has developed to extract data from the Integrated Transport Information System (ITIS) and prepare public transport networks for use in the Sydney Strategic Transport Model

Computing Execution Times with eXecution Decision Diagrams in the Presence of Out-Of-Order Resources

Worst-Case Execution Time (WCET) is a key component for the verification of critical real-time applications. Yet, even the simplest microprocessors implement pipelines with concurrently-accessed resources, such as the memory bus shared by fetch and memory stages. Although their in-order pipelines are, by nature, very deterministic, the bus can cause out-of-order accesses to the memory and, therefore, timing anomalies: local timing effects that can have global effects but that cannot be easily composed to estimate the global WCET. To cope with this situation, WCET analyses have to generate important over-estimations in order to preserve safety of the computed times or have to explicitly track all possible executions. In the latter case, the presence of out-of-order behavior leads to a combinatorial blowup of the number of pipeline states for which efficient state abstractions are difficult to design. This paper proposes instead a compact and exact representation of the timings in the pipeline, using eXecution Decision Diagram (XDD) [1]. We show how XDD can be used to model pipeline states all along the execution paths by leveraging the algebraic properties of XDD. This computational model allows to compute the exact temporal behavior at control flow graph level and is amenable to efficiently and precisely support WCET calculation in presence of out-of-order bus accesses. This model is finally experimented on the TACLe benchmark suite and we observe good performance making this approach appropriate for industrial applications

Worst-Case Energy-Consumption Analysis by Microarchitecture-Aware Timing Analysis for Device-Driven Cyber-Physical Systems

Many energy-constrained cyber-physical systems require both timeliness and the execution of tasks within given energy budgets. That is, besides knowledge on worst-case execution time (WCET), the worst-case energy consumption (WCEC) of operations is essential. Unfortunately, WCET analysis approaches are not directly applicable for deriving WCEC bounds in device-driven cyber-physical systems: For example, a single memory operation can lead to a significant power-consumption increase when thereby switching on a device (e.g. transceiver, actuator) in the embedded system. However, as we demonstrate in this paper, existing approaches from microarchitecture-aware timing analysis (i.e. considering cache and pipeline effects) are beneficial for determining WCEC bounds: We extended our framework on whole-system analysis with microarchitecture-aware timing modeling to precisely account for the execution time that devices are kept (in)active. Our evaluations based on a benchmark generator, which is able to output benchmarks with known baselines (i.e. actual WCET and actual WCEC), and an ARM Cortex-M4 platform validate that the approach significantly reduces analysis pessimism in whole-system WCEC analyses