1,619,660 research outputs found

    PLRU Cache Domino Effects

    Get PDF
    Domino effects have been shown to hinder a tight prediction of worst case execution times (WCET) on real-time hardware. First investigated by Lundqvist and Stenström, domino effects caused by pipeline stalls were shows to exist in the PowerPC by Schneider. This paper extends the list of causes of domino effects by showing that the pseudo LRU (PLRU) cache replacement policy can cause unbounded effects on the WCET. PLRU is used in the PowerPC PPC755, which is widely used in embedded systems, and some x86 models

    Numerical Modeling of AC Loss in HTS Coated Conductors and Roebel Cable Using T-A Formulation and Comparison with H Formulation

    Get PDF
    With recent advances in second-generation high temperature superconductors (2G HTS) and cable technologies, various numerical models based on finite-element method (FEM) have been proposed to help interpret measured AC loss and assist cable design. The T-A formulation, implemented in COMSOL, shows great potential for reducing the overall computation costs. In this paper, the performance of the T-A formulation for calculating the AC loss of coated superconductors and cables were assessed and compared against the widely accepted H formulation, with benchmark model of a single REBCO tape in 2D/3D and a 14-strand Roebel cable. Evaluation and comparison on key metrics including the computation time, the number of degrees of freedom and the numerical accuracy were presented, which could provide a reference for researchers in applying the T-A formulation for AC loss calculation

    How The Timing of Grade Retention Affects Outcomes: Identification and Estimation of Time-Varying Treatment Effects

    Get PDF
    Increasingly, grade retention is viewed as an important alternative to social promotion, yet evidence to date is unable to disentangle how the effect of grade retention varies by abilities and over time. The key challenge is differential selection of students into retention across grades and by abilities. Because existing quasi-experimental methods cannot address this question, we develop a new strategy that is a hybrid between a control function and a generalization of the fixed effects approach. Applying our method to nationally-representative, longitudinal data, we find evidence of dynamic selection into retention and that the treatment effect of retention varies considerably across grades and unobservable abilities of students. Our strategy can be applied more broadly to many time-varying or multiple treatment settings.time-varying treatments, dynamic selection, grade retention, factor analysis

    On Timing Model Extraction and Hierarchical Statistical Timing Analysis

    Full text link
    In this paper, we investigate the challenges to apply Statistical Static Timing Analysis (SSTA) in hierarchical design flow, where modules supplied by IP vendors are used to hide design details for IP protection and to reduce the complexity of design and verification. For the three basic circuit types, combinational, flip-flop-based and latch-controlled, we propose methods to extract timing models which contain interfacing as well as compressed internal constraints. Using these compact timing models the runtime of full-chip timing analysis can be reduced, while circuit details from IP vendors are not exposed. We also propose a method to reconstruct the correlation between modules during full-chip timing analysis. This correlation can not be incorporated into timing models because it depends on the layout of the corresponding modules in the chip. In addition, we investigate how to apply the extracted timing models with the reconstructed correlation to evaluate the performance of the complete design. Experiments demonstrate that using the extracted timing models and reconstructed correlation full-chip timing analysis can be several times faster than applying the flattened circuit directly, while the accuracy of statistical timing analysis is still well maintained

    Timing jitter of passively mode-locked semiconductor lasers subject to optical feedback; a semi-analytic approach

    Get PDF
    We propose a semi-analytical method of calculating the timing fluctuations in mode-locked semiconductor lasers and apply it to study the effect of delayed coherent optical feedback on pulse timing jitter in these lasers. The proposed method greatly reduces computation times and therefore allows for the investigation of the dependence of timing fluctuations over greater parameter domains. We show that resonant feedback leads to a reduction in the timing jitter and that a frequency-pulling region forms about the main resonances, within which a timing jitter reduction is observed. The width of these frequency-pulling regions increases linearly with short feedback delay times. We derive an analytic expression for the timing jitter, which predicts a monotonous decrease in the timing jitter for resonant feedback of increasing delay lengths, when timing jitter effects are fully separated from amplitude jitter effects. For long feedback cavities the decrease in timing jitter scales approximately as 1/τ1/\tau with the increase of the feedback delay time τ\tau
    corecore