PLRU Cache Domino Effects

Domino effects have been shown to hinder a tight prediction of worst case execution times (WCET) on real-time hardware. First investigated by Lundqvist and Stenström, domino effects caused by pipeline stalls were shows to exist in the PowerPC by Schneider. This paper extends the list of causes of domino effects by showing that the pseudo LRU (PLRU) cache replacement policy can cause unbounded effects on the WCET. PLRU is used in the PowerPC PPC755, which is widely used in embedded systems, and some x86 models

On Timing Model Extraction and Hierarchical Statistical Timing Analysis

In this paper, we investigate the challenges to apply Statistical Static Timing Analysis (SSTA) in hierarchical design flow, where modules supplied by IP vendors are used to hide design details for IP protection and to reduce the complexity of design and verification. For the three basic circuit types, combinational, flip-flop-based and latch-controlled, we propose methods to extract timing models which contain interfacing as well as compressed internal constraints. Using these compact timing models the runtime of full-chip timing analysis can be reduced, while circuit details from IP vendors are not exposed. We also propose a method to reconstruct the correlation between modules during full-chip timing analysis. This correlation can not be incorporated into timing models because it depends on the layout of the corresponding modules in the chip. In addition, we investigate how to apply the extracted timing models with the reconstructed correlation to evaluate the performance of the complete design. Experiments demonstrate that using the extracted timing models and reconstructed correlation full-chip timing analysis can be several times faster than applying the flattened circuit directly, while the accuracy of statistical timing analysis is still well maintained

Plugging Side-Channel Leaks with Timing Information Flow Control

The cloud model's dependence on massive parallelism and resource sharing exacerbates the security challenge of timing side-channels. Timing Information Flow Control (TIFC) is a novel adaptation of IFC techniques that may offer a way to reason about, and ultimately control, the flow of sensitive information through systems via timing channels. With TIFC, objects such as files, messages, and processes carry not just content labels describing the ownership of the object's "bits," but also timing labels describing information contained in timing events affecting the object, such as process creation/termination or message reception. With two system design tools-deterministic execution and pacing queues-TIFC enables the construction of "timing-hardened" cloud infrastructure that permits statistical multiplexing, while aggregating and rate-limiting timing information leakage between hosted computations.Comment: 5 pages, 3 figure

Hop Harvest Timing

In the Northeast, hop harvest generally begins in mid-August and continues through mid-September. Harvest date is primarily dependent on the hop variety but weather can delay or hasten maturation and impact when harvest will occur. In addition to weather, various pests, such as spider mites and downy mildew, can similarly impact harvest timing. The time at which you harvest hops can affect the various qualities of your finished product. Alpha and beta acid content peaks before many essential oils have fully developed. Delaying harvest can provide time for these oils to develop but increases the amount of time the hops are left vulnerable to disease and fall rains which can result in degradation of resins

Dissociating Explicit and Implicit Timing in Parkinson\u2019s Disease Patients: Evidence from Bisection and Foreperiod Tasks

A consistent body of literature reported that Parkinson\u2019s disease (PD) is marked by severe deficits in temporal processing. However, the exact nature of timing problems in PD patients is still elusive. In particular, what remains unclear is whether the temporal dysfunction observed in PD patients regards explicit and/or implicit timing. Explicit timing tasks require participants to attend to the duration of the stimulus, whereas in implicit timing tasks no explicit instruction to process time is received but time still affects performance. In the present study, we investigated temporal ability in PD by comparing 20 PD participants and 20 control participants in both explicit and implicit timing tasks. Specifically, we used a time bisection task to investigate explicit timing and a foreperiod task for implicit timing. Moreover, this is the first study investigating sequential effects in PD participants. Results showed preserved temporal ability in PD participants in the implicit timing task only (i.e., normal foreperiod and sequential effects). By contrast, PD participants failed in the explicit timing task as they displayed shorter perceived durations and higher variability compared to controls. Overall, the dissociation reported here supports the idea that timing can be differentiated according to whether it is explicitly or implicitly processed, and that PD participants are selectively impaired in the explicit processing of time

Transforming timing diagrams into knowledge acquisition in automated specification

Requirements engineering is an important part of developing programs. It is an essential stage of the software development process that defines what a product or system should to achieve. The UML Timing diagram and Knowledge Acquisition in Automated Specification (KAOS) model are requirements engineering techniques. KAOS is a goal-oriented requirements approach while the Timing diagram is a graphical notation used for explaining software timing requirements. KAOS uses linear temporal logic (LTL) to describe time constraints in goal and operation models. Similarly, the Timing diagram can describe some temporal operators such as X (next), U (until) and R (release) over some period of time. Thus, our aim is to use the Timing diagram to generate parts of a KAOS model. In this paper we demonstrate techniques for creating a KAOS goal model from a Timing diagram. The Timing diagram which is used in this paper is adapted from the UML 2.0 Timing diagram and includes features to support translation into KAOS. We use a case study of a Lift system as an example to explain the translation processes described here

Global timing: a conceptual framework to investigate the neural basis of rhythm perception in humans and non-human species

Timing cues are an essential feature of music. To understand how the brain gives rise to our experience of music we must appreciate how acoustical temporal patterns are integrated over the range of several seconds in order to extract global timing. In music perception, global timing comprises three distinct but often interacting percepts: temporal grouping, beat, and tempo. What directions may we take to further elucidate where and how the global timing of music is processed in the brain? The present perspective addresses this question and describes our current understanding of the neural basis of global timing perception