Domino effects have been shown to hinder a tight prediction of worst case execution times (WCET) on real-time hardware. First investigated by Lundqvist and StenstrÃ¶m, domino effects caused by pipeline stalls were shows to exist in the PowerPC by Schneider. This paper extends the list of causes of domino effects by showing that the pseudo LRU (PLRU) cache replacement policy can cause unbounded effects on the WCET. PLRU is used in the PowerPC PPC755, which is widely used in embedded systems, and some x86 models

Berg, Christoph

Timing Anomalies

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PLRU Cache Domino EffectsChristoph BergSaarland University, Compiler Design Lab, Saarbru¨cken, Germanycb@cs.uni-sb.deJune 9, 2006AbstractDomino effects have been shown to hinder a tight predictionof worst case execution times (WCET) on real-time hardware.First investigated by Lundqvist and Stenstro¨m, domino effectscaused by pipeline stalls were shown to exist in the PowerPCby Schneider. This paper extends the list of causes of dominoeffects by showing that the pseudo LRU (PLRU) cache re-placement policy can cause unbounded effects on the WCET.PLRU is used in the PowerPC PPC755, which is widely usedin embedded systems, and some x86 models.1 IntroductionEmbedded systems play a key role in any modern product.When employed in safety-critical environments like airbagcontrollers in cars or fly-by-wire systems in air crafts, the tim-ing must meet conditions imposed by the environment. Theexecution time of the tasks running on the embedded pro-cessor must always be lower than a given deadline. Timinganalysis is used to derive an upper bound on the executiontime, called worst case execution time (WCET). Computingthe WCET of a program requires upper bounds for the num-ber of iterations of all loops in the program. On every paththrough the program, the worst case execution times for all in-structions (or alternatively, basic blocks) has to be computedand added up. The longest of these paths is then called thecritical path, and its maximum runtime is the WCET.1.1 Timing AnomaliesIn a simple world, timing analysis could just assume the localworst case for all instructions in a pipeline. When the cachestate is not be precisely known, a memory access not classifiedby the abstract cache state as a cache hit would be considereda cache miss, variable-latency instructions would just take thelongest time, etc. We could then add up all individual timesand get a safe WCET bound.Unfortunately, this is not safe. Out-of-order pipelinesmight reorder instructions such that an longer initial delay(e.g., a cache miss) could cause an overall faster completionof the whole sequence. Similarly, a speedup of an instructioncan lead to a longer runtime for the whole sequence. Thiseffect is called a timing anomaly, and was first described byLundqvist and Stenstro¨m [3, 2].While we can easily get a rough intuition about what a tim-ing anomaly is, a general, hardware-independent definition isdifficult, see [4] for a recent result. We will not detail thedefinition in this paper.1.2 Domino EffectsA special case of timing anomalies is the domino effect, where– after a (possibly empty) prologue – a sequence of instruc-tions is executed in a loop and depending on the initial state ofa component (usually the pipeline, but also the cache, as wewill see later), the loop body runtime will take different valueswithout convergence. The presence of domino effects meansthat we cannot unroll a bounded (or even any) number of iter-ations of a loop and assume in the analysis that the remainingiterations behave the same. Schneider was able to demon-strate actual domino effects caused by the PowerPC PPC755pipeline [5].2 Domino Effects in CachesWe will look at cache behavior when a sequence of memoryaccesses is repeated indefinitely. We will only consider singlecache sets.12.1 FIFOFIFO caches require very little update logic, a round-robincounter points the next way to be replaced. The downside isthat this causes domino effects.Figure 1 shows a 2-way FIFO cache with the access se-quence a-b-c. Starting with an empty cache leads to a repeatedcache content b-c at the end of each iteration, where each cy-cle has 3 cache misses (marked by ‘x’ in the figure). Startingwith c-a in the cache leads to a cycle over 2 iterations with atotal of 3 cache misses, alternatingly 1 and 2 per iteration.21There are cache architectures where the sets are not independent, but thatonly makes timing effects more unpredictable.2This is the same example as in [2].1ECRTS 2006 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysishttp://drops.dagstuhl.de/opus/volltexte/2006/672. . c aa: a . x c ab: b a x b c xc: c b x b ca: a c x a b xb: b a x a bc: c b x c a xa: a c x c ab: b a x b c xc: c b x b ca: a c x a b xb: b a x a bc: c b x c a xFigure 1: 2-way FIFO cache, empty cache is worst case2.2 LRUThe LRU update logic is complex, and LRU caches with morethan 4 ways are rare in practice.LRU caches do not exhibit domino effects. When iteratinga over sequence of instructions, it is easy to see that the cachecontents at the end of the first iteration are the same as at theend of every other iteration. This “memory-less” property ofLRU makes the cache analysis both easy and precise [1].2.3 PLRUPseudo LRU replacement is a variant of LRU where the“ages” of the lines in the cache are not linearly ordered, butarranged in a tree (see Fig. 2). The advantage is that this needsfewer state bits and hence needs a less complex update logic.PLRU has an average case performance comparable to LRU,but the worst case performance, which matters for the WCETprediction, is worse.Heckmann has shown that only 3 to 4 ways of an 8-wayPLRU cache can be tracked in cache analysis [1]. This articleadds domino effects to the list of problems with analyzingPLRU caches.PLRU definition. PLRU maintains a tree of cache ways.Every inner tree node has a bit pointing to the subtree thatcontains the leaf to be replaced next. Figure 2 shows a 4-way example. In the left picture, the three state bits b0, b1, b2point to the second way to be replaced next. In practice, 8-way PLRU is used. The replacement logic is the same, with7 state bits, and an additional level in the tree. For simplicity,we consider 4-way in this article. Note that 2-way PLRU isequivalent to 2-way LRU.On a cache update, and similarly on a cache hit, the statebits on the path leading to the accessed way will be flipped,i.e. making them pointing away from that way. The right pic-ture shows the cache state after the replacement of ‘b’ by ‘e’.The path to the second way consists of bits b0 and b1, so thesehave been flipped.0 10 1 0 10 10 1 0 1b0b1 b2b0b1 b20a c d00a b c d e11 0Figure 2: 4-way PLRUa b c d 0 0 0a: a b c d 1 1 0e: a b e d 0 1 1 xa: a b e d 1 1 1f: a b e f 0 1 0 xa: a b e f 1 1 0g: a b g f 0 1 1 xa: a b g f 1 1 1e: a b g e 0 1 0 xa: a b g e 1 1 0f: a b f e 0 1 1 xa: a b f e 1 1 1g: a b f g 0 1 0 xa: a b f g 1 1 0e: a b e g 0 1 1 xa: a b e g 1 1 1f: a b e f 0 1 0 xa: a b e f 1 1 0g: a b g f 0 1 1 xFigure 3: 4-way PLRU cache, b is never evictedPLRU examples. Figure 3 shows that PLRU does not usethe cache optimally. The access sequence a-e-a-f-a-g containsonly 4 distinct elements, yet 4-PLRU misses for every secondaccess when started with a-b-c-d in the cache.3Figure 4 shows that a PLRU cache can take several itera-tions to stabilize. The fourth iteration is the first that exhibits3 misses as all the following iterations do.Figure 5 shows an example with the access sequence i-f-e-g-i-e-b. The left sequence starts with a-b-c-d in the cache,the right one with an empty cache. For the first two iterations,both caches miss on the same accesses (the cache content iseven the same at the end of the first iteration, though in a dif-ferent order). Starting from the third iteration, the left cachemisses 3 times per iteration, the right cache only 2 times.2.4 Avoiding Domino EffectsThere is no generally safe initial cache state in the contextof domino effects as any state can cause non-converging loopruntimes. With a given program and initial state, we can provethe presence or absence of effects, but in many embedded sys-tem context, modifying the program is infeasible, and the ini-tial state can also be unknown or undefined. Modifying the3Example similar to Fig. 3 in [1].2b e c a 0 0 0c: b e c a 0 0 1a: b e c a 0 0 0b: b e c a 1 1 0e: b e c a 1 0 0b: b e c a 1 1 0c: b e c a 0 1 1d: b d c a 1 0 1 xc: b d c a 0 0 1a: b d c a 0 0 0b: b d c a 1 1 0e: b d e a 0 1 1 xb: b d e a 1 1 1c: b d e c 0 1 0 xd: b d e c 1 0 0c: b d e c 0 0 0a: a d e c 1 1 0 xb: a d b c 0 1 1 xe: a e b c 1 0 1 xb: a e b c 0 0 1c: a e b c 0 0 0d: d e b c 1 1 0 xc: d e b c 0 1 0a: d a b c 1 0 0 xb: d a b c 0 0 1e: e a b c 1 1 1 xb: e a b c 0 1 1c: e a b c 0 1 0d: e d b c 1 0 0 xc: e d b c 0 0 0a: a d b c 1 1 0 xb: a d b c 0 1 1e: a e b c 1 0 1 xb: a e b c 0 0 1c: a e b c 0 0 0d: d e b c 1 1 0 xFigure 4: 4-way PLRU cache, convergence in the forth cyclecompiler not to produce code exhibiting domino effects seemsimpossible, given the simplicity of our FIFO examples.At first glance, it might seem that for PLRU, we can im-prove our knowledge of the cache state by not just taking intoaccount the ordering of the blocks in the cache but also in-clude the tree state bits. However, we can reorder the wayssuch that the tree bits always point left, and modify the cacheupdate accordingly. As with FIFO caches, we will havedomino effects in this simplified cache.3 SummaryTiming anomalies and domino effects cause the complexity oftiming analysis to grow. Several causes are known, this articleadds PLRU caches to the list.To achieve better predictability, some embedded system de-signers lock all but two PLRU ways, leaving a 2-way LRUsubset. We are currently working on cache models that willhopefully be able to extract more precise information from anon-locked cache despite the presence of timing anomalies.a b c d 0 0 0 . . . . 0 0 0i: i b c d 1 1 0 x i . . . 1 1 0 xf: i b f d 0 1 1 x i f . . 1 0 0 xe: i e f d 1 0 1 x i f e . 0 0 1 xg: i e f g 0 0 0 x i f e g 0 0 0 xi: i e f g 1 1 0 i f e g 1 1 0e: i e f g 1 0 0 i f e g 0 1 1b: i e b g 0 0 1 x i b e g 1 0 1 xi: i e b g 1 1 1 i b e g 1 1 1f: i e b f 0 1 0 x i b e f 0 1 0 xe: i e b f 1 0 0 i b e f 0 1 1g: i e g f 0 0 1 x i g e f 1 0 1 xi: i e g f 1 1 1 i g e f 1 1 1e: i e g f 1 0 1 i g e f 0 1 1b: i e g b 0 0 0 x i b e f 1 0 1 xi: i e g b 1 1 0 i b e f 1 1 1f: i e f b 0 1 1 x i b e f 0 1 0e: i e f b 1 0 1 i b e f 0 1 1g: i e f g 0 0 0 x i g e f 1 0 1 xi: i e f g 1 1 0 i g e f 1 1 1e: i e f g 1 0 0 i g e f 0 1 1b: i e b g 0 0 1 x i b e f 1 0 1 xi: i e b g 1 1 1 i b e f 1 1 1f: i e b f 0 1 0 x i b e f 0 1 0e: i e b f 1 0 0 i b e f 0 1 1g: i e g f 0 0 1 x i g e f 1 0 1 xi: i e g f 1 1 1 i g e f 1 1 1e: i e g f 1 0 1 i g e f 0 1 1b: i e g b 0 0 0 x i b e f 1 0 1 xFigure 5: 4-way PLRU cache, domino effect starting in thethird iterationReferences[1] R. Heckmann, M. Langenbach, S. Thesing, and R. Wil-helm. The influence of processor architecture on the de-sign and the results of WCET tools. IEEE Proc., 91(7),July 2003.[2] T. Lundqvist. A WCET Analysis Method for Pipelined Mi-croprocessors with Cache Memories. PhD thesis, Schoolof Computer Science and Engineering, Chalmers Univer-sity of Technology, 2002.[3] T. Lundqvist and P. Stenstro¨m. Timing anomalies indynamically scheduled microprocessors. Number 20 inIEEE Real-Time Systems Sym. (RTSS’99), Dec. 1999.[4] J. Reineke, B. Wachter, S. Thesing, R. Wilhelm, I. Polian,J. Eisinger, and B. Becker. A definition and classificationof timing anomalies. 6th Intl Workshop on Worst-CaseExecution Time (WCET) Analysis, July 2006.[5] J. Schneider. Combined Schedulability and WCET Anal-ysis for Real-Time Operating Systems. PhD thesis, Uni-versita¨t des Saarlandes, Dec. 2002.3

PLRU Cache Domino Effects

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PLRU Cache Domino Effects

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