NEGATIVE BIAS TEMPERATURE INSTABILITY STUDIES FOR ANALOG SOC CIRCUITS

Negative Bias Temperature Instability (NBTI) is one of the recent reliability issues in sub threshold CMOS circuits. NBTI effect on analog circuits, which require matched device pairs and mismatches, will cause circuit failure. This work is to assess the NBTI effect considering the voltage and the temperature variations. It also provides a working knowledge of NBTI awareness to the circuit design community for reliable design of the SOC analog circuit. There have been numerous studies to date on the NBTI effect to analog circuits. However, other researchers did not study the implication of NBTI stress on analog circuits utilizing bandgap reference circuit. The reliability performance of all matched pair circuits, particularly the bandgap reference, is at the mercy of aging differential. Reliability simulation is mandatory to obtain realistic risk evaluation for circuit design reliability qualification. It is applicable to all circuit aging problems covering both analog and digital. Failure rate varies as a function of voltage and temperature. It is shown that PMOS is the reliabilitysusceptible device and NBTI is the most vital failure mechanism for analog circuit in sub-micrometer CMOS technology. This study provides a complete reliability simulation analysis of the on-die Thermal Sensor and the Digital Analog Converter (DAC) circuits and analyzes the effect of NBTI using reliability simulation tool. In order to check out the robustness of the NBTI-induced SOC circuit design, a bum-in experiment was conducted on the DAC circuits. The NBTI degradation observed in the reliability simulation analysis has given a clue that under a severe stress condition, a massive voltage threshold mismatch of beyond the 2mV limit was recorded. Bum-in experimental result on DAC proves the reliability sensitivity of NBTI to the DAC circuitry

Dynamic Lifetime Reliability and Energy Management for Network-on-Chip based Chip Multiprocessors

In this dissertation, we study dynamic reliability management (DRM) and dynamic energy management (DEM) techniques for network-on-chip (NoC) based chip multiprocessors (CMPs). In the first part, the proposed DRM algorithm takes both the computational and the communication components of the CMP into consideration and combines thread migration and dynamic voltage and frequency scaling (DVFS) as the two primary techniques to change the CMP operation. The goal is to increase the lifetime reliability of the overall system to the desired target with minimal performance degradation. The simulation results on a variety of benchmarks on 16 and 64 core NoC based CMP architectures demonstrate that lifetime reliability can be improved by 100% for an average performance penalty of 7.7% and 8.7% for the two CMP architectures. In the second part of this dissertation, we first propose novel algorithms that employ Kalman filtering and long short term memory (LSTM) for workload prediction. These predictions are then used as the basis on which voltage/frequency (V/F) pairs are selected for each core by an effective dynamic voltage and frequency scaling algorithm whose objective is to reduce energy consumption but without degrading performance beyond the user set threshold. Secondly, we investigate the use of deep neural network (DNN) models for energy optimization under performance constraints in CMPs. The proposed algorithm is implemented in three phases. The first phase collects the training data by employing Kalman filtering for workload prediction and an efficient heuristic algorithm based on DVFS. The second phase represents the training process of the DNN model and in the last phase, the DNN model is used to directly identify V/F pairs that can achieve lower energy consumption without performance degradation beyond the acceptable threshold set by the user. Simulation results on 16 and 64 core NoC based architectures demonstrate that the proposed approach can achieve up to 55% energy reduction for 10% performance degradation constraints. Simulation experiments compare the proposed algorithm against existing approaches based on reinforcement learning and Kalman filtering and show that the proposed DNN technique provides average improvements in energy-delay-product (EDP) of 6.3% and 6% for the 16 core architecture and of 7.4% and 5.5% for the 64 core architecture

Electromigration modeling and layout optimization for advanced VLSI

textElectromigration (EM) is a critical problem for interconnect reliability in advanced VLSI design. Because EM is a strong function of current density, a smaller cross-sectional area of interconnects can degrade the EM-related lifetime of IC, which is expected to become more severe in future technology nodes. Moreover, as EM is governed by various factors such as temperature, material property, geometrical shape, and mechanical stress, different interconnect structures can have distinct EM issues and solutions to mitigate them. For example, one of the most prominent technologies, die stacking technology of three-dimensional (3D) ICs, can have different EM problems from that of planer ICs, due to their unique interconnects such as through-silicon vias (TSVs). This dissertation investigates EM in various interconnect structures, and applies the EM models to optimize IC layout. First, modeling of EM is developed for chip-level interconnects, such as wires, local vias, TSVs, and multi-scale vias (MSVs). Based on the models, fast and accurate EM-prediction methods are proposed for the chip-level designs. After that, by utilizing the EM-prediction methods, the layout optimization methods are suggested, such as EM-aware routing for 3D ICs and EM-aware redundant via insertion for the future technology nodes in VLSI. Experimental results show that the proposed EM modeling approaches enable fast and accurate EM evaluation for chip design, and the EM-aware layout optimization methods improve EM-robustness of advanced VLSI designs.Electrical and Computer Engineerin

Process development and reliability of thin gate oxides

The Semiconductor Industry Association\u27s (SIA) current National Technological Roadmap calls for the development of a suitable dielectric material for use in gate oxide for the 0.18|micrometers generation of chips and beyond. Some of the key challenges identified are resistance to oxide trapped charge generation from higher levels of tunneling currents and/or plasma processing, and formation of an effective barrier to dopant penetration during the gate processing. One promising material to meet these challenges is nitrided thermal oxide. Development of a growth process that yields high quality, lOnm thick, thermally grown Si02 films at RJT for use as a gate dielectric is described. Thin oxides (8nm - 20nm) were grown by thermal oxidation followed by inert anneals in Ar and N2. Nitrided oxides were created by implanting N2 (dose range: 5el3 - lei 5 /cm2) into the substrate prior to gate oxidation. Test equipment was setup to study Fowler Nordheim (FN) tunneling and dielectric breakdown. Test structures consisted of conventional and novel MOS capacitor structures with aluminum and poly-silicon gate electrodes. Scaling RJT\u27s existing, 20nm oxidation process to lOnm resulted in degradation of dielectric strength from \u3e lOMV/cm to ~6-7MV/cm for Al-gate MOS capacitors. Replacing the Al gate material with poly-silicon restored the dielectric strength to lOMV/cm. Performing an N2 implant through a screening oxide, prior to gate oxidation, was investigated as a means of obtaining a nitrided thermal oxide. For certain doses (5el3 - 5el4 /cm2), Al-gate MOS capacitors exhibited an improved dielectric strength as the mean value increased from 6- 7MV/cm to ~9MV/cm. Poly-Si gate MOS capacitors showed a similar improvement for the nitrided oxides, exhibiting mean dielectric strength values in the 10-12MV/cm range. Fowler- Nordheim (FN) tunnel current measurements showed that the nitrided films exhibit lower leakage levels and less charge trapping than their thermal Si02 counterparts. Results indicate that a 12nm nitrided oxide, for a certain dose (5el4/cm2), exhibited equivalent electrical performance to a 20nm thermally grown Si02 oxide. In conclusion, a process was developed for yielding reliable thin gate oxides (~10nm) in a university fab

The risk mitigation strategy taxonomy and generated risk event effect neutralization method

In the design of new products and systems, the mitigation of potential failures is very important. The sooner in a product\u27s design mitigation can be performed, the lower the cost and easier to implement those mitigations become. However, currently, most mitigations strategies rely on the expertise of the engineers designing a product, and while models and for failure modes do exist to help, there are no guidelines for performing product changes to reduce risk. To help alleviate this, the risk mitigation strategy taxonomy is created from an empirical collection of mitigation strategies used in industry for failure mitigation, creating a consistent set of definitions for electromechanical risk mitigation strategies. By storing mitigation data in this consistent format, the data can be used to evaluate and compare different mitigation strategies. Applying this, the Generated Risk Event Effect Neutralization (GREEN) method is used to generate mitigation strategies for a product during the conceptual design of the product, where changes are the easiest to implement and cost the least. The GREEN method then compares and selects the best strategy based on the popularity, likelihood change, and consequence change that result from implementing the strategies --Abstract, page iv

GROK-FPGA: Generating Real on-Chip Knowledge for FPGA Fine-Grain Delays Using Timing Extraction

Circuit variation is one of the biggest problems to overcome if Moore\u27s Law is to continue. It is no longer possible to maintain an abstraction of identical devices without huge yield losses, performance penalties, and energy costs. Current techniques such as margining and grade binning are used to deal with this problem. However, they tend to be conservative, offering limited solutions that will not scale as variation increases. Conventional circuits use limited tests and statistical models to determine the margining and binning required to counteract variation. If the limited tests fail, the whole chip is discarded. On the other hand, reconfigurable circuits, such as FPGAs, can use more fine-grained, aggressive techniques that carefully choose which resources to use in order to mitigate variation. Knowing which resources to use and avoid, however, requires measurement of underlying variation. We present Timing Extraction, a methodology that allows measurement of process variation without expensive testers nor highly invasive techniques, rather, relying only on resources already available on conventional FPGAs. It takes advantage of the fact that we can measure the delay of logic paths between any two registers. Measuring enough paths, provides the information necessary to decompose the delay of each path into individual components-essentially, forming a system of linear equations. Determining which paths to measure requires simple graph transformation algorithms applied to a representation of the FPGA circuit. Ultimately, this process decomposes the FPGA into individual components and identifies which paths to measure for computing the delay of individual components. We apply Timing Extraction to 18 commercially available Altera Cyclone III (65 nm) FPGAs. We measure 22×28 logic clusters and the interconnect within and between cluster. Timing Extraction decomposes this region into 1,356,182 components, classified into 10 categories, requiring 2,736,556 path measurements. With an accuracy of ±3.2 ps, our measurements reveal regional variation on the order of 50 ps, systematic variation from 30 ps to 70 ps, and random variation in the clusters with σ=15 ps and in the interconnect with σ=62 ps

Modelling the mechanisms of nitridation of SiC based devices during anneals in NH3 and NO gases

The work presented in this thesis is focused on the mechanisms of processes thatoccur during the NO and NH3anneals of 4H-SiC/a-SiO2devices, specifically on thenitridation of performance limiting defects in a-SiO2. All results are found usingdensity functional theory (DFT) and classical molecular dynamics.The first two results chapters of this thesis investigate the interactions of nitricoxide (NO) and ammonia (NH3) with a pristine a-SiO2network. This investigationis important on two fronts, the first is that the oxide used in these devices is of highquality (CVD oxide), and the second is that these molecules have been shown to in-corporate into the oxide and, in some cases, chemically interact with it. Hence onemust understand the interactions of these molecules with the pristine a-SiO2. My re-sults demonstrate that neutral NO molecules only have steric repulsive interactionswith the pristine network and negative NO molecule interacts with the network Siatoms electrostatically. These interactions manifest as higher NO migration barri-ers in the negative charge state compared to the neutral charge state. Ammonia isshown to form similar interstitials but also react with the surface silanol groups toform smaller ammonia fragments, like NH2and NH, which then lead to nitridationseen in elemental studies of such devices.In the next chapter I examine the interaction of NO and NH3fragments withcommon defects in the a-SiO2network. The results in this chapter show how thecharge transition levels (CTLs) of known oxide defects move deeper into the SiC/a-SiO2band gap, on nitridation, leading to the conclusion that the tunnelling proba-bility to these defects decreases due to the large difference in energy between theSiC CBM and the nitridated defect levels. In the final chapter I present the results of simulations of the structure and properties of a SiC/a-SiO2interface as well asthe effects of proximity of the interface for defect properties. Finally, I discuss thecharacter of surface relaxation of the a-face of 4H-SiC

PROGNOSTICS OF SOLDER JOINT RELIABILITY UNDER VIBRATION LOADING USING PHYSICS OF FAILURE APPROACH

Physics-of-failure (PoF) is an approach that utilizes knowledge of a product's life cycle loading and failure mechanisms to perform reliability modeling, design, and assessment. Prognostics is the process of predicting the future reliability of a system by assessing the extent of deviation or degradation of a product from its expected normal operating states. When prognostics is combined with physics-of-failure models, it is possible to make continuously updated reliability predictions based on the monitoring of the actual environmental and operational conditions of each individual product. A literature review showed that the research on prognostics of solder joint reliability under vibration loading is very limited. However, personal portable electronic products are no longer used exclusively in a benign office environment. For example, any electronic component (throttles, brakes, or steering) in an automobile should be able to survive in a vibration environment. In this thesis, a methodology was developed for monitoring, recording, and analyzing the life-cycle vibration loads for remaining-life prognostics of solder joints. The responses of printed circuit boards (PCB) to vibration loading were monitored using strain gauges and accelerometers, and they were further transferred to solder strain and stress for damage assessment using a failure fatigue model. Damage estimates were accumulated using Miner's rule after every mission and then used to predict the life consumed and the remaining life. The results were verified by experimentally measuring component lives through real-time daisy-chain resistance measurements. This thesis also presents an uncertainty assessment method for remaining life prognostics of solder joints under vibration loading. Basic steps include uncertainty source categorization, sensitivity analysis, uncertainty propagation, and remaining life probability calculation. Five types of uncertainties were categorized, including measurement uncertainty, parameter uncertainty, model uncertainty, failure criteria uncertainty, and future usage uncertainty. Sensitivity analysis was then used to identify the dominant input variables that influence model output. After that, a Monte Carlo simulation was used for uncertainty propagation and to provide a distribution of accumulated damage. From the accumulated damage distributions, the remaining life was then able to be predicted with confidence intervals. The results showed that the experimentally measured failure time was within the bounds of the uncertainty analysis prediction

Magnetron sputtered thin films and composites for automotive and aerospace electrical insulation

Ceramics are highly prised as insulating materials because of their high stability under demanding conditions (thermal, chemical and radiological). However, the use of ceramics as wire insulation is currently limited to powder packed and relatively thick low voltage coatings. This work follows the development of sputtered Al2O3 and Al2O3, SiO2 and Ta2O5 composite films as deposited onto copper. Copper disk studies will ultimately be translated onto Cu wire for a proof of concept study. Initial Al2O3 deposition utilised RF or DC sputtering but this found to have low deposition rate (up to 16 nmh 1) and to contain crystallite and metallic defects (up to 19.6 at. % Al0) respectively. These issues were addressed by introducing pulsed DC (PDC) deposition conditions, producing films with no crystalline or metallic defects (up to 146 nmh 1). The dielectric strength of PDC films measured by AFM time dependant dielectric breakdown was 310 ± 21 Vμm 1, higher than that of the DC deposited films which had a dielectric strength of between 165 ± 19 and 221 ± 20 Vμm 1. A dielectric strength of 310 Vμm 1 is suitable for applications with a voltage rating below 150 V and is also a good platform for the production of higher quality coatings. The mechanical properties of the films did suffer from a lower amount of blending at the interface, DC pull off strength was 25.8 ± 9.8 - 72.3 ± 5.6 MPa with the PDC pull off strength being 55.7 ± 2.9 MPa). Wires coated with such PDC Al2O3 showed promise with full circumference coating, however, short circuiting was apparent in the wires potentially caused by micro cracking induced either during or post deposition. The use of multilayer composites consisting of the aforementioned PDC Al2O3 and RF SiO2 or RF Ta2O5 resulted in significant gains with respect to the material’s electrical properties. The films deposited with 2 layers of each PDC Al2O3 and the RF addition performed best in terms of dielectric strengths of 513 ± 18 and 466 ± 86 Vμm 1 for Ta2O5 and SiO2 composites respectively. The success of the 2x2 layer configuration resulted from a compromise between the number of RF layers and their thickness. The mechanical properties did, however, suffer as a result of increased intrinsic stress caused by the use of multilayers of materials with varying expansion coefficients, reducing pull off adhesion strength to a maximum of 34.4 ± 4.4 MPa, where ideally the pull off adhesion would be above 80 MPa. Heat treatment of these coatings resulted in decreased adhesive properties, with a maximum pull off adhesion strength of 20.1 ± 0.9 MPa being apparent. Most of the electrical properties remained the same or were decreased by heat treatment, however the dielectric strength of the SiO2 composites improved by an average of 12 % resulting in a maximum dielectric strength of 517 ± 24 Vμm 1 due to a reduction in the defect density in the films. Conversely the electrical properties of Ta2O5 composites suffered greatly following heat treatment with a maximum dielectric strength of 358 ± 31 Vμm 1. This was theorised to result from Cu migration from the substrate and the potential for Ta2O5 to crystallise at temperatures close to 500 °C. Coating of Cu wires with PDC alumina was shown to be possible, with coatings of various interlayer and coating thickness. Characterisation showed that the wire coating rig enabled the whole circumference of the wire to be coated with alumina. Tensile testing resulted in transvers cracking followed by longitudinal cracking above an applied strain of 1.5 and 4.0 % respectively. Following heat treatment the copper substrate softened and resulted in delamination failures in the coatings during tensile testing. Electrical testing of the wires was inconsistent due micro cracking in the wire coatings. It has been shown that the use of mixed material composites sputtered by PDC and RF sputtering have potential as high dielectric strength insulating materials, improving upon the base Al2O3 believed to be a result of passivation of structural and compositional defects. Additionally, it has been shown that physical vapour deposition in conjunction with a modified sample holder can be utilised for coating of bare copper wire with the potential to act as isolative coatings