A study of project planning on Libyan construction projects

Construction projects are regularly faced by scheduling problems causing the projects to finish beyond their predetermined due date; this is a global phenomenon. The main purpose of this study is to consider the problems associated with project planning generally, with specific reference to construction projects in Libya. This study is unique in two respects. First, despite the recent high volume of infrastructure work in the country, there have been few investigations into construction delays in Libya. Secondly, earlier studies have considered the causes or the effects of project delays, whereas the present aim is to evaluate the potential of applying a planning and scheduling technique that is entirely novel in the Libyan context. The paper reports the results of Phase I of this research

Efficient FPGA implementation of high-throughput mixed radix multipath delay commutator FFT processor for MIMO-OFDM

This article presents and evaluates pipelined architecture designs for an improved high-frequency Fast Fourier Transform (FFT) processor implemented on Field Programmable Gate Arrays (FPGA) for Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM). The architecture presented is a Mixed-Radix Multipath Delay Commutator. The presented parallel architecture utilizes fewer hardware resources compared to Radix-2 architecture, while maintaining simple control and butterfly structures inherent to Radix-2 implementations. The high-frequency design presented allows enhancing system throughput without requiring additional parallel data paths common in other current approaches, the presented design can process two and four independent data streams in parallel and is suitable for scaling to any power of two FFT size N. FPGA implementation of the architecture demonstrated significant resource efficiency and high-throughput in comparison to relevant current approaches within literature. The proposed architecture designs were realized with Xilinx System Generator (XSG) and evaluated on both Virtex-5 and Virtex-7 FPGA devices. Post place and route results demonstrated maximum frequency values over 400 MHz and 470 MHz for Virtex-5 and Virtex-7 FPGA devices respectively

Improving latency tolerance of multithreading through decoupling

The increasing hardware complexity of dynamically scheduled superscalar processors may compromise the scalability of this organization to make an efficient use of future increases in transistor budget. SMT processors, designed over a superscalar core, are therefore directly concerned by this problem. The article presents and evaluates a novel processor microarchitecture which combines two paradigms: simultaneous multithreading and access/execute decoupling. Since its decoupled units issue instructions in order, this architecture is significantly less complex, in terms of critical path delays, than a centralized out-of-order design, and it is more effective for future growth in issue-width and clock speed. We investigate how both techniques complement each other. Since decoupling features an excellent memory latency hiding efficiency, the large amount of parallelism exploited by multithreading may be used to hide the latency of functional units and keep them fully utilized. The study shows that, by adding decoupling to a multithreaded architecture, fewer threads are needed to achieve maximum throughput. Therefore, in addition to the obvious hardware complexity reduction, it places lower demands on the memory system. The study also reveals that multithreading by itself exhibits little memory latency tolerance. Results suggest that most of the latency hiding effectiveness of SMT architectures comes from the dynamic scheduling. On the other hand, decoupling is very effective at hiding memory latency. An increase in the cache miss penalty from 1 to 32 cycles reduces the performance of a 4-context multithreaded decoupled processor by less than 2 percent. For the nondecoupled multithreaded processor, the loss of performance is about 23 percent.Peer ReviewedPostprint (published version

Development of a scale for factors causing delays in infrastructure projects in India

The objective of the paper is to develop a validated scale to measure the factors that cause delays in infrastructure projects. The study employed a standard three phase scale development procedure of Churchill (1979) which was augmented subsequently by Nunnally, Bernstein and Berge (1994) and Prakash and Phadtare (2018). In phase one, 73 factors that cause delays were identified, which were reduced to 45 based on literature review and expert opinions. These 45 factors were subjected to an exploratory factor analysis (EFA) and confirmatory factor analysis (CFA) in phase two and three, respectively, to refine and establish convergent, discriminant and nomological validity of the scale. The study confirms that delays in infrastructure projects happen due to six factors, i.e., Contractor Related Factors (CON); Consultant Related Factors (CS); External Factors (EX); Labour Related Factors (LR); Material Related Factors (MT) and Design Related Factors (DJ). The study is particularly useful for the firms engaged in the development of infrastructure projects globally, as it identifies and ranks the factors that cause delays in a project. However, the study being confirmatory in nature only confirms the grouping of factors causing delays and is also limited by the possibility of sampling error.&nbsp

funcX: A Federated Function Serving Fabric for Science

Exploding data volumes and velocities, new computational methods and platforms, and ubiquitous connectivity demand new approaches to computation in the sciences. These new approaches must enable computation to be mobile, so that, for example, it can occur near data, be triggered by events (e.g., arrival of new data), be offloaded to specialized accelerators, or run remotely where resources are available. They also require new design approaches in which monolithic applications can be decomposed into smaller components, that may in turn be executed separately and on the most suitable resources. To address these needs we present funcX---a distributed function as a service (FaaS) platform that enables flexible, scalable, and high performance remote function execution. funcX's endpoint software can transform existing clouds, clusters, and supercomputers into function serving systems, while funcX's cloud-hosted service provides transparent, secure, and reliable function execution across a federated ecosystem of endpoints. We motivate the need for funcX with several scientific case studies, present our prototype design and implementation, show optimizations that deliver throughput in excess of 1 million functions per second, and demonstrate, via experiments on two supercomputers, that funcX can scale to more than more than 130000 concurrent workers.Comment: Accepted to ACM Symposium on High-Performance Parallel and Distributed Computing (HPDC 2020). arXiv admin note: substantial text overlap with arXiv:1908.0490

A Scalable Low-Cost-UAV Traffic Network (uNet)

This article proposes a new Unmanned Aerial Vehicle (UAV) operation paradigm to enable a large number of relatively low-cost UAVs to fly beyond-line-of-sight without costly sensing and communication systems or substantial human intervention in individual UAV control. Under current free-flight-like paradigm, wherein a UAV can travel along any route as long as it avoids restricted airspace and altitudes. However, this requires expensive on-board sensing and communication as well as substantial human effort in order to ensure avoidance of obstacles and collisions. The increased cost serves as an impediment to the emergence and development of broader UAV applications. The main contribution of this work is to propose the use of pre-established route network for UAV traffic management, which allows: (i) pre- mapping of obstacles along the route network to reduce the onboard sensing requirements and the associated costs for avoiding such obstacles; and (ii) use of well-developed routing algorithms to select UAV schedules that avoid conflicts. Available GPS-based navigation can be used to fly the UAV along the selected route and time schedule with relatively low added cost, which therefore, reduces the barrier to entry into new UAV-applications market. Finally, this article proposes a new decoupling scheme for conflict-free transitions between edges of the route network at each node of the route network to reduce potential conflicts between UAVs and ensuing delays. A simulation example is used to illustrate the proposed uNet approach.Comment: To be submitted to journal, 21 pages, 9 figure

Survey on wireless technology trade-offs for the industrial internet of things

Aside from vast deployment cost reduction, Industrial Wireless Sensor and Actuator Networks (IWSAN) introduce a new level of industrial connectivity. Wireless connection of sensors and actuators in industrial environments not only enables wireless monitoring and actuation, it also enables coordination of production stages, connecting mobile robots and autonomous transport vehicles, as well as localization and tracking of assets. All these opportunities already inspired the development of many wireless technologies in an effort to fully enable Industry 4.0. However, different technologies significantly differ in performance and capabilities, none being capable of supporting all industrial use cases. When designing a network solution, one must be aware of the capabilities and the trade-offs that prospective technologies have. This paper evaluates the technologies potentially suitable for IWSAN solutions covering an entire industrial site with limited infrastructure cost and discusses their trade-offs in an effort to provide information for choosing the most suitable technology for the use case of interest. The comparative discussion presented in this paper aims to enable engineers to choose the most suitable wireless technology for their specific IWSAN deployment