Optimization Of 5.7 Ghz Class E Power Amplifier For The Application Of Envelope Elimination And Restoration

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2007Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2007Rekabetin yoğun olduğu günümüzde tasarımcılar hafif, boyutları daha küçük ve düşük güçle çalışan yüksek performanslı ürün geliştirmenin yollarını aramaktadırlar. RF alıcı uygulamalarında güç kuvvetlendiricileri en fazla güç sarfiyatının olduğu bölümdür. Kablosuz iletişim sistemlerinde güç küvvetlendiricisi verimi maliyeti direkt olarak etkilemektedir. Teorik olarak %100 verim elde edilebilen E-sınıfı güç kuvvetlendiricileri transistorların açık/kapalı durum geçişlerinde güç sarfiyatını minimize edebilmektedir. Ayrıca çıkış gerilimi kaynak gerilimi ile doğrusal değişmektedir. Bu çalışmada E sınıfı güç kuvvetlendiricilerinin tasarım metodları ele alınmıştır. 5.7 GHz de çalışan birinde toplu devre elemanları, diğerinde transmisyon hattı elemanları kullanımış E sınıfı güç kuvvetlendiricileri tasarlanmıştır. Her iki devrede de %50 güç ekli verim (GEV) ve 500mW çıkış gücü elde edilmiştir. Sinyaldeki bozulmayı azaltmak için başvurulan doğrusallaştırma yöntemi Zarf Yoketme ve Tekrar Oluşturma metodudur. E sınıfı kuvvetlendiricinin Zarf Yoketme ve Tekrar Oluşturma yöntemi kullanılarak doğrusallaştırılmasıyla IMD bileşenlerinde 7.5 dB azalmış olup seviyesi gerçek işaretin 20dB altındadır.In today’s competitive, manufactures and product developers are seeking ways to build high performance devices that are lighter in weight, smaller in size and operating at lower power. In transceiver applications one module is responsible for a large portion of the power consumption - the power amplifier. The efficiency of the power amplifier has a direct impact on the cost of the wireless communication system. The class-E amplifier has a maximum theoretical efficiency of 100%. Class E power amplifiers have the ability to minimize power loss during on/off transitions of the transistor. Also, the output voltage varies linearly with the supply voltage. This thesis describes the design and the linearization methodology of the Class E amplifiers. Two class-E amplifiers operating at 5.7 GHz are presented. One of them is a lumped elements based circuit and the other is a transmission lines based circuit. Both circuit show good performance with 50% PAE and have 500mW output power. Envelope elimination and restoration is the linearization method chosen to achieve reduction of signal distortion. Linearization Class E PA using EER system provides an additional 7.5 dB reduction in intermodulation distortion products, achieving a minimum distortion level of 20 dB below the fundamental signals.Yüksek LisansM.Sc

Nonlinear Design Technique for High-Power Switching-Mode Oscillators

A simple nonlinear technique for the design of high-efficiency and high-power switching-mode oscillators is presented. It combines existing quasi-nonlinear methods and the use of an auxiliary generator (AG) in harmonic balance. The AG enables the oscillator optimization to achieve high output power and dc-to-RF conversion efficiency without affecting the oscillation frequency. It also imposes a sufficient drive on the transistor to enable the switching-mode operation with high efficiency. Using this AG, constant-power and constant-efficiency contour plots are traced in order to determine the optimum element values. The oscillation startup condition and the steady-state stability are analyzed with the pole-zero identification technique. The influence of the gate bias on the output power, efficiency, and stability is also investigated. A class-E oscillator is demonstrated using the proposed technique. The oscillator exhibits 75 W with 67% efficiency at 410 MHz

Analog dithering techniques for highly linear and efficient transmitters

The current thesis is about investigation of new methods and techniques to be able to utilize the switched mode amplifiers, for linear and efficient applications. Switched mode amplifiers benefit from low overlap between the current and voltage wave forms in their output terminals, but they seriously suffer from nonlinearity. This makes it impossible to use them to amplify non-constant envelope message signals, where very high linearity is expected. In order to do that, dithering techniques are studied and a full linearity analysis approach is developed, by which the linearity performance of the dithered amplifier can be analyzed, based on the dithering level and frequency. The approach was based on orthogonalization of the equivalent nonlinearity and is capable of prediction of both co-channel and adjacent channel nonlinearity metrics, for a Gaussian complex or real input random signal. Behavioral switched mode amplifier models are studied and new models are developed, which can be utilized to predict the nonlinear performance of the dithered power amplifier, including the nonlinear capacitors effects. For HFD application, self-oscillating and asynchronous sigma delta techniques are currently used, as pulse with modulators (PWM), to encode a generic RF message signal, on the duty cycle of an output pulse train. The proposed models and analysis techniques were applied to this architecture in the first phase, and the method was validated with measurement on a prototype sample, realized in 65 nm TSMC CMOS technology. Afterwards, based on the same dithering phenomenon, a new linearization technique was proposed, which linearizes the switched mode class D amplifier, and at the same time can reduce the reactive power loss of the amplifier. This method is based on the dithering of the switched mode amplifier with frequencies lower than the band-pass message signal and is called low frequency dithering (LFD). To test this new technique, two test circuits were realized and the idea was applied to them. Both of the circuits were of the hard nonlinear type (class D) and are integrated CMOS and discrete LDMOS technologies respectively. The idea was successfully tested on both test circuits and all of the linearity metric predictions for a digitally modulated RF signal and a random signal were compared to the measurements. Moreover a search method to find the optimum dither frequency was proposed and validated. Finally, inspired by averaging interpretation of the dithering phenomenon, three new topologies were proposed, which are namely DLM, RF-ADC and area modulation power combining, which are all nonlinear systems linearized with dithering techniques. A new averaging method was developed and used for analysis of a Gilbert cell mixer topology, which resulted in a closed form relationship for the conversion gain, for long channel devices

Highly efficient linear CMOS power amplifiers for wireless communications

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.PhDCommittee Chair: Kenney, J. Stevenson; Committee Member: Jongman Kim; Committee Member: Kohl, Paul A.; Committee Member: Kornegay, Kevin T.; Committee Member: Lee, Chang-H

DESIGN OF A GAAS DISTRIBUTED AMPLIFIER WITH LC TRAPS BASED BROADBAND LINEARIZATION

Increasing the linearity of power amplifiers has been an important area of research because its signal integrity influences the performance of the entire transreceiver system and there are strict regulatory requirements on them. Due to the nonlinear behaviour of power amplifiers, third order intermodulation products are generated close to the desired signals and cannot be removed by filters. Increasing linearity will help bring these distortion products closer to the noise floor. However, it is not an easy task to increase linearity without trading off output power. To maintain the same level of output power generated but with higher linearity, many techniques, each with its own pros and cons, have been implemented to linearize an amplifier. Techniques involving feedback are seriously limited in terms of modulation bandwidth whereas methods such as predistortion and feedforward are very difficult to implement. This project seeks to use a simple method of placing terminations directly to the distributed amplifier (DA), making it a device level linearization technique and can be used in addition to the other system level techniques mentioned earlier. To increase linearity over a broad bandwidth of 0.5 to 3.0 GHz, this work proposes using low impedance terminations (LC traps) at the envelope frequency to the input and output of several distributed amplifiers. This research is novel since this is the first time broadband improvement in linearity has been demonstrated using the LC trap method. Two design iterations were completed (first design iteration has four variants to test the output trap while the second design iteration has three variants to test the input trap). The low impedance terminations are implemented using inductor-capacitor networks that are external to the monolithic microwave integrated circuit (MMIC). Design and layout of the DAs were carried out using Agilent’s Advanced Design System (ADS). Results show that placing the traps at the output of the DA does not truly affect the linearity of the device at lower frequencies but provide an improvement of 1.6 dB and 3.4 dB to the third-order output intercept point (OIP3) at 2.5 GHz and 3.0 GHz, respectively. With traps at the input, measurement results at -5 dBm input power, viii 1.375 V base bias (61 mA total collector current) and 10 MHz two tone spacing show a broadband improvement throughout the band (0.5 GHz to 3.0 GHz) of 3.3 dB to 7.4 dB in OIP3. Furthermore, the OIP3 is increased to 19.2 dB above P1dB. Results show that the improvement in OIP3 comes without lowering gain, return loss or P1dB and without causing any stability problems

Transmissor RF de elevado rendimento com duas entradas digitais para sistemas 5G

In recent years, there has been a need to increase the capacity and speed of information transmission, so the communication signals used in mobile communications have been improved to meet the expectations. This will be even more significant in future 5G systems, since due to the high expansion of wireless devices, current 4G systems are starting to push their limits, where only small improvements can be achieved. Which complicates the design of transmitters, since these new signals have a wider bandwidth and a large variation between their average and peak value, causing amplifiers to operate most of the time in a zone where they are not as efficient. For this reason, amplifier architectures not only aim to have high efficiency when operating at maximum signal excursion, but also to increase efficiency in the zone where they will operate most of the time. For this purpose, there are architectures based on supply voltage modulation and load modulation to improve the efficiency at lower powers. This work addresses load modulation architectures, where Doherty and Chireix are the most prominent. In addition, with the increase in digital signal processing capabilities, new amplification architectures based on the load modulation technique have recently been proposed, but instead of using only one RF input, they use two independent digitally controlled inputs. This dissertation aims at implementing a Doherty-Chireix amplifier with two digital inputs to achieve efficient amplification for the 1.7 to 2.4GHz frequency band. In the end it was possible to design and implement a Doherty-Chireix power amplifier, with 700MHz bandwidth, with a gain between 13.9-11.3dB, a maximum power of 45dBm, a PAE of over 60% and peak-to-average power ratio between 5.2-4.1dB.Nos últimos anos, tem havido uma necessidade de aumentar a capacidade e velocidade de transmissão de informação, deste modo os sinais de comunicação utilizados nas comunicações móveis têm evoluído por forma a corresponder as expectativas. Tal será ainda mais significativo nos futuros sistemas 5G, já que devido à elevada expansão de dispositivos sem fio, os atuais sistemas 4G estão a começar a atingir os seus limites, onde apenas pequenas melhorias podem ser alcançadas. Isto vem complicar o projeto dos transmissores, uma vez que estes novos sinais apresentam uma maior largura de banda e uma grande variação entre o seu valor médio e de pico, fazendo com que os amplificadores operem na maior parte do tempo numa zona em que não são tão eficientes. Por esta razão, as arquiteturas de amplificação nos dias de hoje não só visam ter um grande rendimento quando operam com a máxima excursão de sinal, mas também o aumento do rendimento na zona onde irão operar a maior parte do tempo. Nesse sentido existem arquiteturas baseadas em modelação de tensão de alimentação e modelação de carga de modo a melhorar a eficiência a potências mais baixas. Neste trabalho são abordadas arquiteturas de modulação de carga, onde Doherty e Chireix são as que mais se destacam. Para além disso, com o aumento da capacidade de processamento digital de sinal, recentemente foram propostas novas arquiteturas de amplificação que se baseiam nestas técnicas, mas em vez de utilizar apenas uma entrada de RF, usam duas entradas independentes controladas digitalmente. Esta dissertação visa a implementação de um amplificador Doherty-Chireix com duas entras digitais de modo a obter uma amplificação eficiente para uma banda de frequências de 1.7 a 2.4GHz. No final foi possível projetar e implementar um amplificador de potência Doherty-Chireix, com 700MHz de largura de banda, com um ganho compreendido entre 13.9-11.3dB, potência máxima de 45dBm, uma PAE superior a 60% e peak-to-average power ratio entre 5.2-4.1dB.Mestrado em Engenharia Eletrónica e Telecomunicaçõe

Analysis and design of ΣΔ Modulators for Radio Frequency Switchmode Power Amplifiers

Power amplifiers are an integral part of every basestation, macrocell, microcell and mobile phone, enabling data to be sent over the distances needed to reach the receiver’s antenna. While linear operation is needed for transmitting WCDMA and OFDM signals, linear operation of a power amplifier is characterized by low power efficiency, and contributes to unwanted power dissipation in a transmitter. Recently, a switchmode power amplifier operation was considered for reducing power losses in a RF transmitter. A linear and efficient operation of a PA can be achieved when the transmitted RF signal is ΣΔ modu- lated, and subsequently amplified by a nonlinear device. Although in theory this approach offers linearity and efficiency reaching 100%, the use of ΣΔ modulation for transmitting wideband signals causes problems in practical implementation: it requires high sampling rate by the digital hardware, which is needed for shaping large contents of a quantization noise induced by the modulator but also, the binary output from the modulator needs an RF power amplifier operating over very wide frequency band. This thesis addresses the problem of noise shaping in a ΣΔ modulator and nonlinear distortion caused by broadband operation in switchmode power amplifier driven by a ΣΔ modulated waveform. The problem of sampling rate increase in a ΣΔ modulator is solved by optimizing structure of the modulator, and subsequent processing of an input signal’s samples in parallel. Independent from the above, a novel technique for reducing quan- tization noise in a bandpass ΣΔ modulator using single bit quantizer is presented. The technique combines error pulse shaping and 3-level quantization for improving signal to noise ratio in a 2-level output. The improvement is achieved without the increase of a digital hardware’s sampling rate, which is advantageous also from the perspective of power consumption. The new method is explored in the course of analysis, and verified by simulated and experimental results. The process of RF signal conversion from the Cartesian to polar form is analyzed, and a signal modulator for a polar transmitter with a ΣΔ-digitized envelope signal is designed and implemented. The new modulator takes an advantage of bandpass digital to analog conversion for simplifying the analog part of the modulator. A deformation of the pulsed RF signal in the experimental modulator is demonstrated to have an effect primarily on amplitude of the RF signal, which is correctable with simple predistortion

Development and Implementation of a VHF High Power Amplifier for the Multi-Channel Coherent Radar Depth Sounder/Imager System

This thesis presents the implementation and characterization of a VHF high power amplifier developed for the Multi-channel Coherent Radar Depth Sounder/Imager (MCoRDS/I) system. MCoRDS/I is used to collect data on the thickness and basal topography of polar ice sheets, ice sheet margins, and fast-flowing glaciers from airborne platforms. Previous surveys have indicated that higher transmit power is needed to improve the performance of the radar, particularly when flying over challenging areas. The VHF high power amplifier system presented here consists of a 50-W driver amplifier and a 1-kW output stage operating in Class C. Its performance was characterized and optimized to obtain the best tradeoff between linearity, output power, efficiency, and conducted and radiated noise. A waveform pre-distortion technique to correct for gain variations (dependent on input power and operating frequency) was demonstrated using digital techniques. The amplifier system is a modular unit that can be expanded to handle a larger number of transmit channels as needed for future applications. The system can support sequential transmit/receive operations on a single antenna by using a high-power circulator and a duplexer circuit composed of two 90° hybrid couplers and anti-parallel diodes. The duplexer is advantageous over switches based on PIN-diodes due to the moderately high power handling capability and fast switching time. The system presented here is also smaller and lighter than previous implementations with comparable output power levels