VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Overcoming the Challenges for Multichip Integration: A Wireless Interconnect Approach

The physical limitations in the area, power density, and yield restrict the scalability of the single-chip multicore system to a relatively small number of cores. Instead of having a large chip, aggregating multiple smaller chips can overcome these physical limitations. Combining multiple dies can be done either by stacking vertically or by placing side-by-side on the same substrate within a single package. However, in order to be widely accepted, both multichip integration techniques need to overcome significant challenges. In the horizontally integrated multichip system, traditional inter-chip I/O does not scale well with technology scaling due to limitations of the pitch. Moreover, to transfer data between cores or memory components from one chip to another, state-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the target chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. On the other hand, in vertically integrated multichip system, the high power density resulting from the placement of computational components on top of each other aggravates the thermal issues of the chip leading to degraded performance and reduced reliability. Liquid cooling through microfluidic channels can provide cooling capabilities required for effective management of chip temperatures in vertical integration. However, to reduce the mechanical stresses and at the same time, to ensure temperature uniformity and adequate cooling competencies, the height and width of the microchannels need to be increased. This limits the area available to route Through-Silicon-Vias (TSVs) across the cooling layers and make the co-existence and co-design of TSVs and microchannels extreamly challenging. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects are capable of establishing radio communications within as well as between multiple chips. The primary goal of this dissertation is to propose design principals targeting both horizontally and vertically integrated multichip system to provide high bandwidth, low latency, and energy efficient data communication by utilizing mm-wave wireless interconnects. The proposed solution has two parts: the first part proposes design methodology of a seamless hybrid wired and wireless interconnection network for the horizontally integrated multichip system to enable direct chip-to-chip communication between internal cores. Whereas the second part proposes a Wireless Network-on-Chip (WiNoC) architecture for the vertically integrated multichip system to realize data communication across interlayer microfluidic coolers eliminating the need to place and route signal TSVs through the cooling layers. The integration of wireless interconnect will significantly reduce the complexity of the co-design of TSV based interconnects and microchannel based interlayer cooling. Finally, this dissertation presents a combined trade-off evaluation of such wireless integration system in both horizontal and vertical sense and provides future directions for the design of the multichip system

Energy challenges for ICT

The energy consumption from the expanding use of information and communications technology (ICT) is unsustainable with present drivers, and it will impact heavily on the future climate change. However, ICT devices have the potential to contribute signi - cantly to the reduction of CO2 emission and enhance resource e ciency in other sectors, e.g., transportation (through intelligent transportation and advanced driver assistance systems and self-driving vehicles), heating (through smart building control), and manu- facturing (through digital automation based on smart autonomous sensors). To address the energy sustainability of ICT and capture the full potential of ICT in resource e - ciency, a multidisciplinary ICT-energy community needs to be brought together cover- ing devices, microarchitectures, ultra large-scale integration (ULSI), high-performance computing (HPC), energy harvesting, energy storage, system design, embedded sys- tems, e cient electronics, static analysis, and computation. In this chapter, we introduce challenges and opportunities in this emerging eld and a common framework to strive towards energy-sustainable ICT

Josephson Junctions and SQUIDs Based on CVD Graphene

Josephson junctions and superconducting quantum interference devices (SQUIDs) with graphene as the weak link between the superconductors have been intensely studied in recent years, with respect to both fundamental physics and potential applications. Since the carrier density and resistivity of graphene are heavily dependent on the Fermi level, Josephson junctions and SQUIDs with graphene as the weak link can have their I-V properties easily tuned by the gate voltage. However, most of the previous work on superconductor-graphene-superconductor (SGS) Josephson junctions and SQUIDs was based on mechanically exfoliated graphene, which is not compatible with wafer-scale production. In this project, we have greatly improved the availability and applicability of graphene-based Josephson junctions and SQUIDs. We developed a method to fabricate Josephson junctions and SQUIDs with graphene grown by chemical vapour deposition (CVD) as the weak link. We demonstrate that very short, wide CVD-graphene-based Josephson junctions with Nb electrodes can work without any undesirable hysteresis in the electrical characteristics from 1.5 K down to a base temperature of 320 mK, and the critical current can be effectively tuned by the gate voltage by up to an order of magnitude. As a result, dc SQUIDs made up of these junctions can have their critical current tuned by both the magnetic field and the gate voltage. We also obtained evidence for ballistic transport in SGS junctions as short as 50 nm. We found that even for junction as wide as 80 µm, the critical current shows an ideal Fraunhofer-like interference pattern in a perpendicular magnetic field, indicating the distribution of supercurrent is uniform. We studied the definition of Josephson penetration depth, and proposed a new formula for 2D coplanar junctions

Scanning electrochemical cell microscopy : a versatile technique for nanoscale electrochemistry and functional imaging

Scanning electrochemical cell microscopy (SECCM) is a new pipette-based imaging technique purposely designed to allow simultaneous electrochemical, conductance, and topographical visualization of surfaces and interfaces. SECCM uses a tiny meniscus or droplet, confined between the probe and the surface, for high-resolution functional imaging and nanoscale electrochemical measurements. Here we introduce this technique and provide an overview of its principles, instrumentation, and theory. We discuss the power of SECCM in resolving complex structure-activity problems and provide considerable new information on electrode processes by referring to key example systems, including graphene, graphite, carbon nanotubes, nanoparticles, and conducting diamond. The many longstanding questions that SECCM has been able to answer during its short existence demonstrate its potential to become a major technique in electrochemistry and interfacial science

Event program

UNLV Undergraduates from all departments, programs and colleges participated in a campus-wide symposium on April 16, 2011. Undergraduate posters from all disciplines and also oral presentations of research activities, readings and other creative endeavors were exhibited throughout the festival

Memristive Non-Volatile Memory Based on Graphene Materials

Resistive random access memory (RRAM), which is considered as one of the most promising next-generation non-volatile memory (NVM) devices and a representative of memristor technologies, demonstrated great potential in acting as an artificial synapse in the industry of neuromorphic systems and artificial intelligence (AI), due its advantages such as fast operation speed, low power consumption, and high device density. Graphene and related materials (GRMs), especially graphene oxide (GO), acting as active materials for RRAM devices, are considered as a promising alternative to other materials including metal oxides and perovskite materials. Herein, an overview of GRM-based RRAM devices is provided, with discussion about the properties of GRMs, main operation mechanisms for resistive switching (RS) behavior, figure of merit (FoM) summary, and prospect extension of GRM-based RRAM devices. With excellent physical and chemical advantages like intrinsic Young’s modulus (1.0 TPa), good tensile strength (130 GPa), excellent carrier mobility (2.0 × 105 cm2∙V−1∙s−1), and high thermal (5000 Wm−1∙K−1) and superior electrical conductivity (1.0 × 106 S∙m−1), GRMs can act as electrodes and resistive switching media in RRAM devices. In addition, the GRM-based interface between electrode and dielectric can have an effect on atomic diffusion limitation in dielectric and surface effect suppression. Immense amounts of concrete research indicate that GRMs might play a significant role in promoting the large-scale commercialization possibility of RRAM devices