Theory, Modelling and Implementation of Graphene Field-Effect Transistor

PhDTwo-dimensional materials with atomic thickness have attracted a lot of attention from researchers worldwide due to their excellent electronic and optical properties. As the silicon technology is approaching its limit, graphene with ultrahigh carrier mobility and ultralow resistivity shows the potential as channel material for novel high speed transistor beyond silicon. This thesis summarises my Ph.D. work including the theory and modelling of graphene field-effect transistors (GFETs) as well as their potential RF applications. The introduction and review of existing graphene transistors are presented. Multiscale modelling approaches for graphene devices are also introduced. A novel analytical GFET model based on the drift-diffusion transport theory is then developed for RF/microwave circuit analysis. Since the electrons and holes have different mobility variations against the channel potential in graphene, the ambipolar GFET cannot be modelled with constant carrier mobility. A new carrier mobility function, which enables the accurate modelling of the ambipolar property of GFET, is hence developed for this purpose. The new model takes into account the carrier mobility variation against the bias voltage as well as the mobility difference between electrons and holes. It is proved to be more accurate for the DC current calculation. The model has been written in Verilog-A language and can be import into commercial software such as Keysight ADS for circuit simulation. In addition, based on the proposed model two GFET non-Foster circuits (NFCs) are conducted. As a negative impedance element, NFCs find their applications in impedance matching of electrically small antennas and bandwidth improvement of metasurfaces. One of the NFCs studied in this thesis is based on the Linvill's technique in which a pair of identical GFETs is used while the other circuit utilises the negative resistance of a single GFET. The stability analysis of NFCs is also presented. Finally, a high impedance surface loaded with proposed NFCs is also studied, demonstrating significant bandwidth enhancement.Engineering and Physical Sciences Research Council (EPSRC) Grant on `Graphene Flexible Electronics and Optoelectronics' (EP/K01711X/1), the EU Graphene Flagship (FP7-ICT-604391) and Graphene Core 1 (H2020 696656

Multi-layer graphene FET compact circuit-level model with temperature effects

This paper presents a circuit-level model of a dual-gate bilayer and four layer graphene field effect transistor (GFET). The model provides an accurate estimation of the conductance at the charge neutrality point (CNP). At the CNP the device has its maximum resistance, at which the model is validated against experimental data of the device off-current for a range of electric fields perpendicular to the channel. The model shows a good agreement for validations carried out at constant and varying temperatures. Using the general Schottky equation, the model estimates the amount of bandgap opening created by the application of an electric field. Also the model shows good agreement when validated against experiment for the channel output conductance against varying gate voltage for both a bilayer and four layer graphene channel

Modelling of field-effect transistors based on 2D materials targeting high-frequency applications

New technologies are necessary for the unprecedented expansion of connectivity and communications in the modern technological society. The specific needs of wireless communication systems in 5G and beyond, as well as devices for the future deployment of Internet of Things has caused that the International Technology Roadmap for Semiconductors, which is the strategic planning document of the semiconductor industry, considered since 2011, graphene and related materials (GRMs) as promising candidates for the future of electronics. Graphene, a one-atom-thick of carbon, is a promising material for high-frequency applications due to its intrinsic superior carrier mobility and very high saturation velocity. These exceptional carrier transport properties suggest that GRM-based field-effect transistors could potentially outperform other technologies. This thesis presents a body of work on the modelling, performance prediction and simulation of GRM-based field-effect transistors and circuits. The main goal of this work is to provide models and tools to ease the following issues: (i) gaining technological control of single layer and bilayer graphene devices and, more generally, devices based on 2D materials, (ii) assessment of radio-frequency (RF) performance and microwave stability, (iii) benchmarking against other existing technologies, (iv) providing guidance for device and circuit design, (v) simulation of circuits formed by GRM-based transistors.Comment: Thesis, 164 pages, http://hdl.handle.net/10803/40531

Material properties analysis of graphene base transistor (GBT) for VLSI analog circuits design

Graphene base transistor’s (GBT) analysis has been reviewed in this paper. This study has been focused on work carried out by other authors for GBT physics. Here prominence has been given to material properties and their effects on GBT for VLSI analog circuit design to operate in high frequency range of THz. Various papers in literature have been reported for the implementation of designs with different emitter and collector materials. Materials properties are the controlling parameters to decide cut-off frequency (f­T), trans-conductance, gain and off current (Ioff) in GBT. The implemented results of literatures signify that the electron affinity and work function of emitter and collector are the dominant factors for flow of charges from emitter to collector. Dependency of these two parameters on dielectric constant and thickness of emitter-base insulator (EBI) and base collector insulator (BCI) that are tantalum pentoxide (Ta2O5), carbon-doped silicon oxide (SiCOH) and SiO2 has been studied. Effects of collector and BCI thickness have been investigated in detail to scrutinize base leakage current by the virtue of back scattering in collector-BCI interface. Small signal equivalent circuit model for GBT have also been studied by including parasitic capacitance behaviour between graphene Dirac-point potential with respect to graphene fermi level, emitter, EBI, BCI and collector fermi level potential

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Reconfigurable Reflectarrays and Array Lenses for Dynamic Antenna Beam Control: A Review

Advances in reflectarrays and array lenses with electronic beam-forming capabilities are enabling a host of new possibilities for these high-performance, low-cost antenna architectures. This paper reviews enabling technologies and topologies of reconfigurable reflectarray and array lens designs, and surveys a range of experimental implementations and achievements that have been made in this area in recent years. The paper describes the fundamental design approaches employed in realizing reconfigurable designs, and explores advanced capabilities of these nascent architectures, such as multi-band operation, polarization manipulation, frequency agility, and amplification. Finally, the paper concludes by discussing future challenges and possibilities for these antennas.Comment: 16 pages, 12 figure