3,710 research outputs found
Retransmission of water resources data using the ERTS-1 data collection system
There are no author-identified significant results in this report
Development and analysis of the Software Implemented Fault-Tolerance (SIFT) computer
SIFT (Software Implemented Fault Tolerance) is an experimental, fault-tolerant computer system designed to meet the extreme reliability requirements for safety-critical functions in advanced aircraft. Errors are masked by performing a majority voting operation over the results of identical computations, and faulty processors are removed from service by reassigning computations to the nonfaulty processors. This scheme has been implemented in a special architecture using a set of standard Bendix BDX930 processors, augmented by a special asynchronous-broadcast communication interface that provides direct, processor to processor communication among all processors. Fault isolation is accomplished in hardware; all other fault-tolerance functions, together with scheduling and synchronization are implemented exclusively by executive system software. The system reliability is predicted by a Markov model. Mathematical consistency of the system software with respect to the reliability model has been partially verified, using recently developed tools for machine-aided proof of program correctness
The IceCube Neutrino Observatory: Instrumentation and Online Systems
The IceCube Neutrino Observatory is a cubic-kilometer-scale high-energy
neutrino detector built into the ice at the South Pole. Construction of
IceCube, the largest neutrino detector built to date, was completed in 2011 and
enabled the discovery of high-energy astrophysical neutrinos. We describe here
the design, production, and calibration of the IceCube digital optical module
(DOM), the cable systems, computing hardware, and our methodology for drilling
and deployment. We also describe the online triggering and data filtering
systems that select candidate neutrino and cosmic ray events for analysis. Due
to a rigorous pre-deployment protocol, 98.4% of the DOMs in the deep ice are
operating and collecting data. IceCube routinely achieves a detector uptime of
99% by emphasizing software stability and monitoring. Detector operations have
been stable since construction was completed, and the detector is expected to
operate at least until the end of the next decade.Comment: 83 pages, 50 figures; updated with minor changes from journal review
and proofin
Fibre-optic delivery of time and frequency to VLBI station
The quality of Very Long Baseline Interferometry (VLBI) radio observations
predominantly relies on precise and ultra-stable time and frequency (T&F)
standards, usually hydrogen masers (HM), maintained locally at each VLBI
station. Here, we present an operational solution in which the VLBI
observations are routinely carried out without use of a local HM, but using
remote synchronization via a stabilized, long-distance fibre-optic link. The
T&F reference signals, traceable to international atomic timescale (TAI), are
delivered to the VLBI station from a dedicated timekeeping laboratory.
Moreover, we describe a proof-of-concept experiment where the VLBI station is
synchronized to a remote strontium optical lattice clock during the
observation.Comment: 8 pages, 8 figures, matches the version published in A&A, section
Astronomical instrumentatio
NEGATIVE BIAS TEMPERATURE INSTABILITY STUDIES FOR ANALOG SOC CIRCUITS
Negative Bias Temperature Instability (NBTI) is one of the recent reliability issues in
sub threshold CMOS circuits. NBTI effect on analog circuits, which require matched
device pairs and mismatches, will cause circuit failure. This work is to assess the
NBTI effect considering the voltage and the temperature variations. It also provides a
working knowledge of NBTI awareness to the circuit design community for reliable
design of the SOC analog circuit. There have been numerous studies to date on the
NBTI effect to analog circuits. However, other researchers did not study the
implication of NBTI stress on analog circuits utilizing bandgap reference circuit. The
reliability performance of all matched pair circuits, particularly the bandgap reference,
is at the mercy of aging differential. Reliability simulation is mandatory to obtain
realistic risk evaluation for circuit design reliability qualification. It is applicable to all
circuit aging problems covering both analog and digital. Failure rate varies as a
function of voltage and temperature. It is shown that PMOS is the reliabilitysusceptible
device and NBTI is the most vital failure mechanism for analog circuit in
sub-micrometer CMOS technology. This study provides a complete reliability
simulation analysis of the on-die Thermal Sensor and the Digital Analog Converter
(DAC) circuits and analyzes the effect of NBTI using reliability simulation tool. In
order to check out the robustness of the NBTI-induced SOC circuit design, a bum-in
experiment was conducted on the DAC circuits. The NBTI degradation observed in
the reliability simulation analysis has given a clue that under a severe stress condition,
a massive voltage threshold mismatch of beyond the 2mV limit was recorded. Bum-in
experimental result on DAC proves the reliability sensitivity of NBTI to the DAC
circuitry
InSb charge coupled infrared imaging device: The 20 element linear imager
The design and fabrication of the 8585 InSb charge coupled infrared imaging device (CCIRID) chip are reported. The InSb material characteristics are described along with mask and process modifications. Test results for the 2- and 20-element CCIRID's are discussed, including gate oxide characteristics, charge transfer efficiency, optical mode of operation, and development of the surface potential diagram
SIRU development. Volume 1: System development
A complete description of the development and initial evaluation of the Strapdown Inertial Reference Unit (SIRU) system is reported. System development documents the system mechanization with the analytic formulation for fault detection and isolation processing structure; the hardware redundancy design and the individual modularity features; the computational structure and facilities; and the initial subsystem evaluation results
Limits on Fundamental Limits to Computation
An indispensable part of our lives, computing has also become essential to
industries and governments. Steady improvements in computer hardware have been
supported by periodic doubling of transistor densities in integrated circuits
over the last fifty years. Such Moore scaling now requires increasingly heroic
efforts, stimulating research in alternative hardware and stirring controversy.
To help evaluate emerging technologies and enrich our understanding of
integrated-circuit scaling, we review fundamental limits to computation: in
manufacturing, energy, physical space, design and verification effort, and
algorithms. To outline what is achievable in principle and in practice, we
recall how some limits were circumvented, compare loose and tight limits. We
also point out that engineering difficulties encountered by emerging
technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl
Fault tolerant data management system
Described in detail are: (1) results obtained in modifying the onboard data management system software to a multiprocessor fault tolerant system; (2) a functional description of the prototype buffer I/O units; (3) description of modification to the ACADC and stimuli generating unit of the DTS; and (4) summaries and conclusions on techniques implemented in the rack and prototype buffers. Also documented is the work done in investigating techniques of high speed (5 Mbps) digital data transmission in the data bus environment. The application considered is a multiport data bus operating with the following constraints: no preferred stations; random bus access by all stations; all stations equally likely to source or sink data; no limit to the number of stations along the bus; no branching of the bus; and no restriction on station placement along the bus
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