Metalorganic chemical vapor deposition growth and thermal stability of the AllNN/GaN high electron mobility transistor structure

Cataloged from PDF version of article.The AlxIn1-xN barrier high electron mobility transistor (HEMT) structure has been optimized with varied barrier composition and thickness grown by metalorganic chemical vapor deposition. After optimization, a transistor structure comprising a 7 nm thick nearly lattice-matched Al0.83In0.17 N barrier exhibits a sheet electron density of 2.0 x 10(13) cm(-2) with a high electron mobility of 1540 cm(2) V-1 s(-1). AnAl(0.83)In(0.17)N barrier HEMT device with 1 mu m gate length provides a current density of 1.0 A mm(-1) at V-GS = 0 V and an extrinsic transconductance of 242 mS mm(-1), which are remarkably improved compared to that of a conventional Al0.3Ga0.7N barrier HEMT. To investigate the thermal stability of the HEMT epi-structures, post-growth annealing experiments up to 800 degrees C have been applied to Al0.83In0.17N and Al0.3Ga0.7N barrier heterostructures. As expected, the electrical properties of an Al0.83In0.17N barrier HEMT structure showed less stability than that of an Al0.3Ga0.7N barrier HEMT to the thermal annealing. The structural properties of Al0.83In0.17N/GaN also showed more evidence for decomposition than that of the Al0.3Ga0.7N/GaN structure after 800 degrees C post-annealing

A study of semi-insulating GaN grown on AlN buffer/sapphire substrate by metalorganic chemical vapor deposition

We report the remarkably improved crystal quality of semi-insulating GaN grown by metalorganic chemical vapor deposition on an AlN buffer layer, which is deposited on sapphire substrate. The electrical and structural properties are characterized by dark current-voltage transmission line model and X-ray diffraction measurements. It is found that the crystal quality of the GaN epilayer is strongly related with the growth temperature of the decreased-temperature GaN interlayer. In comparison with the normal GaN grown on sapphire, the crystal quality is remarkably improved along with a semi-insulating electrical character. The high-mobility field effect transistors device based on the semi-insulating GaN shows good pinch off properties. Our electrical measurement results of GaN grown directly on an AlN buffer indicated that the as-grown-undoped GaN is naturally semi-insulating material. The origination of the residual donors in normal GaN grown on sapphire substrate is also discussed. © 2006 Elsevier B.V. All rights reserved

Design of III-Nitride Hot Electron Transistors

III-Nitride based devices have made great progress over the past few decades in electronics and photonics applications. As the technology and theoretical understanding of the III-N system matures, the limitations on further development are based on very basic electronic properties of the material, one of which is electron scattering (or ballistic electron effects). This thesis explores the design space of III-N based ballistic electron transistors using novel design, growth and process techniques. The hot electron transistor (HET) is a unipolar vertical device that operates on the principle of injecting electrons over a high-energy barrier (ϕBE) called the emitter into an n-doped region called base and finally collecting the high energy electrons (hot electrons) over another barrier (ϕBC) called the collector barrier. The injected electrons traverse the base in a quasi-ballistic manner. Electrons that get scattered in the base contribute to base current. High gain in the HET is thus achieved by enabling ballistic transport of electrons in the base. In addition, low leakage across the collector barrier (IBCleak) and low base resistance (RB) are needed to achieve high performance. Because of device attributes such as vertical structure, ballistic transport and low-resistance n-type base, the HET has the potential of operating at very high frequencies. Electrical measurements of a HET structure can be used to understand high-energy electron physics and extract information like mean free path in semiconductors. The III-Nitride material system is particularly suited for HETs as it offers a wide range of ΔEcs and polarization charges which can be engineered to obtain barriers which can inject hot-electrons and have low leakage at room temperature. In addition, polarization charges in the III-N system can be engineered to obtain a high-density and high-mobility 2DEG in the base, which can be used to reduce base resistance and allow vertical scaling. With these considerations in mind, III-N HETs had been explored in our research group earlier and gave us encouraging common base IV characteristics. Common emitter transistor operation was, however, not observed due to high RB and IBCleak. This thesis discusses several design and process challenges associated with the HET in general and specific to the III-N system. Many of these challenges like RB, IBCleak, and high energy injection were solved using novel combinations of hetero-structure and polarization engineering, device fabrication, and growth. Common-Emitter operation (with current gain ~ 0.1) was demonstrated in III-N HETs for the first time using injection and collector barriers induced by AlGaN and InGaN polarization-dipoles. In order to improve current gain, different parts of the III-N HET base which contribute to scattering, were identified. A novel base contact methodology using selective etching of GaN with respect to AlN was developed to enable base scaling. Aggressive scaling of all parts of the base was then used to increase current gain. A maximum gain of ~3.5 was demonstrated using a 1.5nm AlN layer as the emitter, 2nm GaN base and 2nm In0.2Ga0.8N as the collector P-D. This is the highest reported DC current gain in III-N HETs to date. The III-N HET structure was also used to extract the mean free path of hot-electrons (λmfp = 6nm) in GaN. The extracted value of mean free path has significant implications for any scaled devices which use ballistic or quasi-ballistic electron transport. We believe that the work presented in this dissertation provides a pathway for high gain in III-N HETs and eventual realization of their high frequency potential

GaN Power Devices: Discerning Application-Specific Challenges and Limitations in HEMTs

GaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is extended for low voltage devices ( \u3c 100 V), presenting results to optimize both lateral features and vertical features. For low voltage design, simulation work suggests that breakdown is more reliant on punch-through as the primary breakdown mechanism rather than on vertical leakage current as is the case with high-voltage devices. A fabrication process flow has been developed for fabricating Schottky-gate, and MIS-HEMT structures at UCF in the CREOL cleanroom. The fabricated devices were designed to validate the simulation work for low voltage GaN devices. The UCF fabrication process is done with a four layer mask, and consists of mesa isolation, ohmic recess etch, an optional gate insulator layer, ohmic metallization, and gate metallization. Following this work, the fabrication process was transferred to the National Nano Device Laboratories (NDL) in Hsinchu, Taiwan, to take advantage of the more advanced facilities there. Following fabrication, a study has been performed on defect induced performance degradation, leading to the observation of a new phenomenon: trap induced negative differential conductance (NDC). Typically NDC is caused by self-heating, however by implementing a substrate bias test in conjunction with pulsed I-V testing, the NDC seen in our fabricated devices has been confirmed to be from buffer traps that are a result of poor channel carrier confinement during the dc operating condition

Optimization of Ohmic Contacts and Surface Passivation for ‘Buffer-Free’ GaN HEMT Technologies

Gallium nitride high electron mobility transistors (GaN HEMTs) draw attention from high frequency and high power industries due to unique properties including high electron mobility and saturation velocity combined with high breakdown voltage. This makes GaN HEMTs suitable for power devices with high switching speed and high frequency applications with high power density requirements. However, the device performance is still partly limited by problems associated with the formation of low resistivity ohmic contact, trapping effects, and the confinement of the two-dimensional electron gas (2DEG).\ua0\ua0\ua0 In this work, reproducible deeply recessed Ta-based ohmic contacts with a low contact resistance of 0.2 - 0.3 Ωmm, a low annealing temperature of 550 - 600 \ub0C, and a large process window were optimized. Low annealing temperature reduces the risk of 2DEG degradation and promotes better morphology of the ohmic contacts. Deeply recessed ohmic contacts beyond the barrier layers make the process less sensitive to the etching depth since the ohmic contacts are formed on the sidewall of the recess. The concept of deeply recessed low resistivity ohmic contacts is also successfully demonstrated on different epi-structures with different barrier designs.\ua0\ua0\ua0 Passivation with silicon nitride (SiN) is an effective method to suppress electron trapping effects. Low Pressure Chemical Vapor Deposition (LPCVD) of SiN has shown to result in high quality dielectrics with excellent passivation effect. However, the surface traps are not fully removed after passivation due to dangling-bonds and native oxide layer at the interface of passivation and epi-structure. Therefore, a plasma-free in-situ NH3 pretreatment method before the deposition of the SiN passivation was studied. The samples with the pretreatment present a 38% lower surface-related current collapse and a 50% lower dynamic on-resistance than the samples without the pretreatment. The improved dynamic performance and lower dispersion directly yield a 30% higher output power of (3.4 vs. 2.6 W/mm) and a better power added efficiency (44% vs. 39%) at 3 GHz. Furthermore, it was found that a longer pretreatment duration improves the uniformity of device performance.\ua0\ua0\ua0 Traditionally, decreasing leakage currents in the buffer and improving electron confinement to the 2DEG are achieved by intentional acceptor-like dopants (iron and carbon) in the GaN buffer and back-barrier layer made by a ternary III-nitride material. However, electron trapping effects and thermal resistivity increase due to the dopants and the ternary material, respectively. In this thesis, a novel approach, where a unique epitaxial scheme permits a thickness reduction of the unintentional-doped (UID) GaN layer down to 250 nm, as compared to a normal thickness of 2 μm. In this way, the AlN nucleation layer effectively act as a back-barrier. The approached, named QuanFINE is investigated and benchmarked to a conventional epi-structure with a thick Fe-doped-GaN buffer. A 2DEG mobility of 2000 cm^2/V-s and the 2DEG concentration of 1.1∙10^13 cm^-2 on QuanFINE indicate that the 2DEG properties are not sacrificed with a thin UID-GaN layer. Thanks to the thin UID-GaN layer of QuanFINE, trapping effects are reduced. Comparable output power of 4.1 W/mm and a PAE of 40% at 3 GHz of both QuanFINE and conventional Fe-doped thick GaN buffer sample are measured

GaN heterojunction FET device Fabrication, Characterization and Modeling

This dissertation is focused on the research efforts to develop the growth, processing, and modeling technologies for GaN-based Heterojunction Field Effect Transistors (HFETs). The interest in investigating GaN HFETs is motivated by the advantageous material properties of nitride semiconductor such as large band gap, large breakdown voltage, and high saturation velocity, which make it very promising for the high power and microwave applications. Although enormous progress has been made on GaN transistors in the past decades, the technologies for nitride transistors are still not mature, especially concerning the reliability and stability of the device. In order to improve the device performance, we first optimized the growth and fabrication procedures for the conventional AlGaN barrier HFET, on which high carrier mobility and sheet density were achieved. Second, the AlInN barrier HFET was successfully processed, with which we obtained improved I-V characteristics compared with conventional structure. The lattice-matched AlInN barrier is beneficial in the removal of strain, which leads to better carrier transport characteristics. Furthermore, new device structures have been examined, including recess-gate HFET with n+ GaN cap layer and gate-on-insulator HFET, among which the insertion of gate dielectrics helps to leverage both DC and microwave performances. In order to depict the microwave behavior of the HFET, small signal modeling approaches were used to extract the extrinsic and intrinsic parameters of the device. An 18-element equivalent circuit model for GaN HFET has been proposed, from which various extraction methods have been tested. Combining the advantages from the cold-FET measurements and hot-FET optimizations, a hybrid extraction method has been developed, in which the parasitic capacitances were attained from the cold pinch-off measurements while the rest of the parameters from the optimization routine. Small simulation error can be achieved by this method over various bias conditions, demonstrating its capability for the circuit level design applications for GaN HFET. Device physics modeling, on the other hand, can help us to reveal the underlying physics for the device to operate. With the development of quantum drift-diffusion modeling, the self-consistent solution to the Schrödinger-Poisson equations and carrier transport equations were fulfilled. Lots of useful information such as band diagram, potential profile, and carrier distribution can be retrieved. The calculated results were validated with experiments, especially on the AlInN layer structures after considering the influence from the parasitic Ga-rich layer on top of the spacer. Two dimensional cross-section simulation shows that the peak of electrical field locates at the gate edge towards the drain, and of different kinds of structures the device with gate field-plate was found to efficiently reduce the possibility of breakdown failure