CMOS TECHNOLOGY: CHALANGES FOR FUTURE DEVELOPMENT

Od pojave tehnologije integriranog sklopa, elektronička industrija bilježi nezapamćen razvoj, vršeći snažan utjecaj na pomorstvo. Posljednjih dvadesetak godina razvoj elektroničke industrije zasnovan je na CMOS VLSI tehnologiji. Neprekidni napredak CMOS VLSI tehnologije omogućen je kontinuiranim smanjivanjem dimenzija MOS tranzistora. Rezultat skaliranja je veća gustoća pakiranja komponenata po elektroničkom sklopu, veća brzina rada i manja disipacija snage po tranzistoru. Današnji su tranzistori 20 puta brži te zauzimaju 1% prostora u odnosu na tranzistore proizvedene prije 20 godina. Očito je da smanjivanje površine tranzistora ne može ići u beskonačnost. Ovim radom se istražuju potencijalna ograničenja razvoja CMOS tehnologije.Since the invention of the integrated circuit technologies, there has been an unprecedented growth of the electronic industry, with significant impact on the maritime industry. In the last twenty years and so, the strongest growth area of the electronic industry has been in CMOS VLSI technology. The sustained growth in CMOS VLSI technology is fueled by a continued shrinking of transistors to ever smaller dimensions. The benefits of miniaturization are higher packing densities, higher circuit speeds, and lower power dissipation. The transistors manufactured today are 20 time faster and occupy less than 1% of the area of those built 20 years ago. It is obvious that a continued reduction of the transistor area cannot sustain forever. This paper examines issues related to the future development of CMOS technology

Development and applications of inkjet printed conducting polymer micro-rings

A drying sessile drop moves the solute particles to the periphery where they get deposited in the form of a ring. This phenomenon is prevalent even with micro drops falling at high velocity from a piezo-actuator based inkjet printer. In polymer microelectronic field, this phenomenon is a major challenge for fabricating devices using inkjet printing. We exploited this problem and applied it for various novel applications in the field of polymer microelectronics. Various dispensing techniques and temperature variations for micro-drop printing were used for modifying the micro-drops in such a way that the periphery of the micro-ring holds most of the solute as compared to inner base layer. Reactive ion etching (RIE) was used for removing the inner base layer in order to make the micro-rings completely hollow from the center. These micro-rings were applied in the fabrication of polymer light emitting diode, humidity sensor and vertical channel field effect transistor. High resolution polymer light emitting diode array (\u3e200 pixels/inch) was fabricated by inkjet printing of micro-ring and each micro-ring acts as a single pixel. These micro-rings were applied as a platform for layer-by-layer (LbL) nano-assembly of poly-3,4-ethylenedioxythiophene:poly-styrenesulfonate (PEDOT:PSS) for the fabrication of humidity sensor. Enhanced sensitivity of the humidity sensor was obtained when the inkjet printed micro-rings are combined with LbL assembled PEDOT:PSS films. During the fabrication of vertical channel field effect transistors, inkjet printed PEDOT:PSS micro-rings were used as source and the inner spacers between the adjacent micro-rings were used to make channel. These micro-rings can also find other applications in the field of biological sciences. These micro-rings can be used as cell culture plates and as scaffolds for cell and/or tissue growth

Electrochemical fabrication of semiconductor nanostructure arrays for photonic applications

Theoretical and experimental investigations of the properties of semiconductor nanostructures have been an active area of research due to the enhanced performance that is observed when electrons and holes are spatially confined in one, two or three dimensions. However, the development of viable photonic devices using this phenomenon requires the development of appropriate fabrication techniques that can provide control over nanostructure size, material composition, and periodicity for structures with dimensions less than 20 nm. To address these challenges, a nanostructure synthesis technique has been developed that is based on the self-organization of nanometer scale pores during the anodization of aluminum thin films. This template can then be used for direct synthesis of semiconductor material, or as a pattern transfer mask for the etching of structures in a semiconductor substrate.;In this work, alumina template technology has been transferred from the exclusive use of an aluminum substrate to a thin film technology that can be applied to an arbitrary substrate material. This thin film process has been developed and characterized to permit control and uniformity over both nanostructure length and diameter. In addition, a Al/Pt/Si structure has been developed to permit direct DC synthesis of semiconductor nanostructures. Finally, the ability of this template to serve as a mask for direct etching of nanoscale features on a semiconductor substrate has been evaluated. This technology is currently being developed to provide device applications in the area of photovoltaic devices and silicon electro-optic modulators

Microstructure and processing effects on stress and reliability for through-silicon vias (TSVs) in 3D integrated circuits

Copper (Cu) Through-silicon via (TSV) is a key enabling element that provides the vertical connection between stacked dies in three-dimensional (3D) integration. The thermal expansion mismatch between Cu and Si induces complex stresses in and around the TSV structures, which can degrade the performance and reliability of 3DICs and are key concerns for technology development. In this dissertation, the effects of Cu microstructure and processing conditions on the stress characteristics and reliability of the TSV structure are studied. First, the stress characteristics of Cu TSV structures are investigated using the substrate curvature method. The substrate curvature measurement was supplemented by microstructure and finite element analyses (FEA) to investigate the mechanisms for the linear and nonlinear stress-temperature behaviors observed for the TSV structure. Implications of the near surface stress on carrier mobility change and device keep-out zone (KOZ) are discussed. Second, via extrusion, an important yield and reliability issue for 3D integration, is analyzed. Synchrotron x-ray microdiffraction technique was introduced for direct measurements of local stress and material behaviors in and around the TSV. Local plasticity near the top of the via was observed which provided direct experimental evidence to support the plasticity mechanism of via extrusion. An analytical model and FEA were used to analyze via extrusion based on local plasticity. Next, the effect of Cu microstructure effect on the thermomechanical behaviors of TSVs is investigated. The contribution from grain boundary and interfacial diffusion on via extrusion and the relaxation mechanisms are discussed. Potential approaches to minimize via extrusion are proposed. Finally, the stress characteristics of 3D die stack structures are studied using synchrotron x-ray microdiffraction. High resolution stress mappings were performed and verified by finite element analysis (FEA). FEA was further developed to estimate the stress effect on device mobility changes and the warpage of the integrated structure.Materials Science and Engineerin

One-dimensional photonic crystal / photonic wire cavities based on silicon-on-insulator (SOI)

It has been of major interest in recent research to produce faster optical processing for many telecommunications applications, as well as other applications of high performance optoelectronics. The combination of one-dimensional photonic crystal structures (PhC) and narrow photonic wire (PhW) waveguides in high refractive-index contrast materials such as silicon-on-insulator (SOI) is one of the main contenders for provision of various compact devices on a single chip. This development is due to the ability of silicon technology to support monolithic integration of optical interconnects and form fully functional photonic devices incorporated into CMOS chips. The high index contrast of the combination of a silicon core with a surrounding cladding of silica and/or air provides strong optical confinement, leading to the realization of more compact structures and small device volumes. In order to obtain a wide range of device functionality, the reduction of propagation losses in narrow wires is equally important, although there are still performance limitations determined by fabrication processes. Compact single-row PhC structures embedded in PhW waveguide micro-cavities could become essential components for wavelength selective devices, especially for possible application in WDM systems. The high quality factor, Q, and confinement of light in a small volume, V, are important for optical signal processing and filtering purposes, implying large Purcell factor values. In this thesis, one-dimensional photonic crystal/photonic wire micro-cavities have been designed and modeled using both 2D and 3D versions of the finite-difference time-domain (FDTD) approach. These devices were fabricated using electron beam lithography (EBL) and reactive ion etching (RIE) for patterning of the silicon layer. The device structures were characterized with TE polarized light, using a tunable laser covering the range from 1480 nm to 1585 nm. Single-row periodic hole-type PhC mirrors consisting of identical and equally spaced holes were embedded in 500 nm wire waveguides. Two PhC hole mirrors were separated with a cavity spacer varying from 400 nm to 500 nm in length to form a micro-cavity. In contrast, several different cavity arrangements were also successfully investigated, - i.e. extended cavity and coupled micro-cavity structures. The experimental results on photonic crystal/photonic wire micro-cavity structures have demonstrated that further enhancement of the quality-factor (Q-factor) - up to approximately 149,000 at wavelengths in the fibre telecommunications range is possible. The Q factor values and the useful transmission levels achieved are due, in particular, to the combination of both tapering within and outside the micro-cavity, with carefully designed hole diameters and non-periodic hole placement within the tapered sections. On the other hand, a large resonance quality factor of approximately 18,500, together with high normalized transmission of 85% through the use of tapering on both sides of the hole-type PhC mirrors that formed the micro-cavity, has been obtained. For the extended cavity case, the multiple resonances excited within the stop band, together with substantial tuning capability of the resonances obtained by varying the cavity length has been demonstrated, together with a Q-factor value of approximately 74,000 at the selected resonance frequency with a normalised transmission of 40%. In addition, the coupled micro-cavity structures considered in this thesis have formed the basic building block for designing multiple cavity structures where the combination of several cavities splits the selected single cavity resonance frequency into a number of resonances that depends directly on the number of cavities used in the design. The coupling strength between the resonators and the Free Spectral Range (FSR) between the split resonance frequencies of the coupled cavity combination were controlled via the use of different numbers of periodic hole structures – and through the use of different aperiodic hole taper arrangements between the two cavities in the middle section of the mirrors

Microbridge Formation for Low Resistance Interline Connection Using Pulsed Laser Techniques

MakeLink® technology has been applied in many semiconductor devices to achieve high performance. Sometimes one-type-link design doesn't make desirous links for all IC manufacturing processes. In this work, four new structures, called microbridge, were designed to form all types of link. Laser processing experiments were performed to verify the designs. The results show that two-lower-level-metal-line design has higher performance (low link resistance), higher productivity (broad energy window), and higher yield than the three-lower-level-metal-line design. Therefore, it can be considered as the optimal design from the processing point of view. Two-lower-level-metal-line with lateral gap structure provides better scalability and it can be used in next generation ICs. If high-speed is the primary concern, an advanced-lateral structure is best, corresponding to its much lower resistance. The reliability tests indicate that the median-times-to-failure of all test structures are greater than nine years in operating condition, presenting reasonable lifetimes for integrated circuits used in the market. A two-dimensional finite element plane models for microbridge formation is developed. Results are compared to the experiments with process windows to present their consistence. The model allowed for using different geometric parameters and metal-dielectric combinations optimizing the design. An optimal design diagram for the Al/SiO2 system is created to provide the designer with criteria to avoid the failure of structure. Trade-off requirements, such as process window and structure size, are also provided. Guidelines are obtained for the Cu/Low-K dielectric system