Cost modelling and concurrent engineering for testable design

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.As integrated circuits and printed circuit boards increase in complexity, testing becomes a major cost factor of the design and production of the complex devices. Testability has to be considered during the design of complex electronic systems, and automatic test systems have to be used in order to facilitate the test. This fact is now widely accepted in industry. Both design for testability and the usage of automatic test systems aim at reducing the cost of production testing or, sometimes, making it possible at all. Many design for testability methods and test systems are available which can be configured into a production test strategy, in order to achieve high quality of the final product. The designer has to select from the various options for creating a test strategy, by maximising the quality and minimising the total cost for the electronic system. This thesis presents a methodology for test strategy generation which is based on consideration of the economics during the life cycle of the electronic system. This methodology is a concurrent engineering approach which takes into account all effects of a test strategy on the electronic system during its life cycle by evaluating its related cost. This objective methodology is used in an original test strategy planning advisory system, which allows for test strategy planning for VLSI circuits as well as for digital electronic systems. The cost models which are used for evaluating the economics of test strategies are described in detail and the test strategy planning system is presented. A methodology for making decisions which are based on estimated costing data is presented. Results of using the cost models and the test strategy planning system for evaluating the economics of test strategies for selected industrial designs are presented

Design for testability in hardware-software systems

Clearly, in today's complex systems, hardware and software approaches to DFT must work together to achieve a successful overall solution. The authors investigate existing and new concepts that may lead to a single design for test strategy in the futur

Crypto-test-lab for security validation of ECC co-processor test infrastructure

© 20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksElliptic Curve Cryptography (ECC) is a technology for public-key cryptography that is becoming increasingly popular because it provides greater speed and implementation compactness than other public-key technologies. Calculations, however, may not be executed by software, since it would be so time consuming, thus an ECC co-processor is commonly included to accelerate the speed. Test infrastructure in crypto co-processors is often avoided because it poses serious security holes against adversaries. However, ECC co-processors include complex modules for which only functional test methodologies are unsuitable, because they would take an unacceptably long time during the production test. Therefore, some internal test infrastructure is always included to permit the application of structural test techniques. Designing a secure test infrastructure is quite a complex task that relies on the designer's experience and on trial & error iterations over a series of different types of attacks. Most of the severe attacks cannot be simulated because of the demanding computational effort and the lack of proper attack models. Therefore, prototypes are prepared using FPGAs. In this paper, a Crypto-Test-Lab is presented that includes an ECC co-processor with flexible test infrastructure. Its purpose is to facilitate the design and validation of secure strategies for testing in this type of co-processor.Postprint (author's final draft

Design-for-delay-testability techniques for high-speed digital circuits

The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud getting more and more important

Developing VLSI Curricula in Electrical and Computer Engineering Department

© ASEE 2010VLSI (Very Large Scale Integrated Circuits) technology has enabled the information technology revolution which greatly changed the life style of human society. Computers, internet, cellphones, digital cameras/camcorders and many other consumer electronic products are powered by VLSI technology. In the past decades, the VLSI industry was constantly driven by the miniaturization of transistors. As governed by Moore’s law, the number of transistors in the same chip area has been doubled every 12 to 18 months. Nowadays, a typical VLSI CPU chip can contain millions to billions of transistors. As a result, the design of VLSI system is becoming more and more complex. Various EDA tools must be used to help the design of modern VLSI chips. The semiconductor and VLSI industry remain strong needs for VLSI engineers each year. In this paper, efforts in developing systematic VLSI curricula in Electrical and Computer Engineering department have been proposed. The goal of the curricula is to prepare students to satisfy the growing demands of VLSI industry as well as the higher education/research institutions. Modern VLSI design needs a thorough understanding about VLSI in device, gate, module and system levels. We developed CPEG/EE 448D: Introduction to VLSI to give students a comprehensive introduction about digital VLSI design and analysis. In this course, various EDA tools (such as Mentor Graphics tools, Cadence PSPICE, Synopsys) are used in the course projects to help students practice the VLSI design. In addition, analog and mixed signal circuit design are becoming more and more important as MEMS (Microelectromechanical Systems) and Nano devices are integrated with VLSI into Systemon-Chip (SoC) design. We developed CPEG/EE 458: Analog VLSI to introduce the analog and mixed signal VLSI design. As portable electronics (e.g. laptops, cellphones, PDAs, digital cameras) becoming more and more popular, low power VLSI circuit design is becoming a hot field. We developed CPEG/EE 548: Low Power VLSI Circuit Design to introduce various low power techniques to reduce the power consumption of VLSI circuits. Nowadays the VLSI circuits can contain billions of transistors, the testing of such complex system becoming more and more challenging. We developed CPEG/EE 549: VLSI Testing to introduce various VLSI testing strategies for modern VLSI design. In addition to the design and testing, we also developed EE 448: Microelectronic Fabrication to introduce the fabrication processes of modern VLSI circuits. With such a series of VLSI related curricula, students have an opportunity to learn comprehensive knowledge and hands-on experience about VLSI circuit design, testing, fabrication and EDA tools. Students demonstrate tremendous interests in the VLSI field, and all the VLSI courses are generally oversubscripted by students in the early stage of enrollment. Many students are also doing the VLSI graduate research and published various papers/posters in the VLSI related journals/conferences

Efficient Path Delay Test Generation with Boolean Satisfiability

This dissertation focuses on improving the accuracy and efficiency of path delay test generation using a Boolean satisfiability (SAT) solver. As part of this research, one of the most commonly used SAT solvers, MiniSat, was integrated into the path delay test generator CodGen. A mixed structural-functional approach was implemented in CodGen where longest paths were detected using the K Longest Path Per Gate (KLPG) algorithm and path justification and dynamic compaction were handled with the SAT solver. Advanced techniques were implemented in CodGen to further speed up the performance of SAT based path delay test generation using the knowledge of the circuit structure. SAT solvers are inherently circuit structure unaware, and significant speedup can be availed if structure information of the circuit is provided to the SAT solver. The advanced techniques explored include: Dynamic SAT Solving (DSS), Circuit Observability Don’t Care (Cir-ODC), SAT based static learning, dynamic learnt clause management and Approximate Observability Don’t Care (ACODC). Both ISCAS 89 and ITC 99 benchmarks as well as industrial circuits were used to demonstrate that the performance of CodGen was significantly improved with MiniSat and the use of circuit structure

High level behavioural modelling of boundary scan architecture.

This project involves the development of a software tool which enables the integration of the IEEE 1149.1/JTAG Boundary Scan Test Architecture automatically into an ASIC (Application Specific Integrated Circuit) design. The tool requires the original design (the ASIC) to be described in VHDL-IEEE 1076 Hardware Description Language. The tool consists of the two major elements: i) A parsing and insertion algorithm developed and implemented in 'C'; ii) A high level model of the Boundary Scan Test Architecture implemented in 'VHDL'. The parsing and insertion algorithm is developed to deal with identifying the design Input/Output (I/O) terminals, their types and the order they appear in the ASIC design. It then attaches suitable Boundary Scan Cells to each I/O, except power and ground and inserts the high level models of the full Boundary Scan Architecture into the ASIC without altering the design core structure