Update of an early warning fault detection method using artificial intelligence techniques

This presentation describes a research investigation to access the feasibility of using an Artificial Intelligence (AI) method to predict and detect faults at an early stage in power systems. An AI based detector has been developed to monitor and predict faults at an early stage on particular sections of power systems. The detector for this early warning fault detection device only requires external measurements taken from the input and output nodes of the power system. The AI detection system is capable of rapidly predicting a malfunction within the system. Artificial Neural Networks (ANNs) are being used as the core of the fault detector. In an earlier paper [11], a computer simulated medium length transmission line has been tested by the detector and the results clearly demonstrate the capability of the detector. Today’s presentation considers a case study illustrating the suitability of this AI Technique when applied to a distribution transformer. Furthermore, an evolutionary optimisation strategy to train ANNs is also briefly discussed in this presentation, together with a ‘crystal ball’ view of future developments in the operation and monitoring of transmission systems in the next millennium

Early warning fault detection using artificial intelligent methods

This paper describes a research investigation to access the feasibility of using an Artificial Intelligence (AI) method to predict and detect faults at an early stage in power systems. An AI based detector has been developed to monitor and predict faults at an early stage on particular sections of power systems. The detector for this early warning fault detection device only requires external measurements taken from the input and output nodes of the power system. The AI detection system is capable of rapidly predicting a malfunction within the system. Artificial Neural Networks (ANNs) are being used as the core of the fault detector. A simulated medium length transmission line has been tested by the detector and the results demonstrate the capability of the detector. Furthermore, comments on an evolutionary technique as the optimisation strategy for ANNs are included in this paper

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

Advanced information processing system: Local system services

The Advanced Information Processing System (AIPS) is a multi-computer architecture composed of hardware and software building blocks that can be configured to meet a broad range of application requirements. The hardware building blocks are fault-tolerant, general-purpose computers, fault-and damage-tolerant networks (both computer and input/output), and interfaces between the networks and the computers. The software building blocks are the major software functions: local system services, input/output, system services, inter-computer system services, and the system manager. The foundation of the local system services is an operating system with the functions required for a traditional real-time multi-tasking computer, such as task scheduling, inter-task communication, memory management, interrupt handling, and time maintenance. Resting on this foundation are the redundancy management functions necessary in a redundant computer and the status reporting functions required for an operator interface. The functional requirements, functional design and detailed specifications for all the local system services are documented

The Parallel Persistent Memory Model

We consider a parallel computational model that consists of $P$ processors, each with a fast local ephemeral memory of limited size, and sharing a large persistent memory. The model allows for each processor to fault with bounded probability, and possibly restart. On faulting all processor state and local ephemeral memory are lost, but the persistent memory remains. This model is motivated by upcoming non-volatile memories that are as fast as existing random access memory, are accessible at the granularity of cache lines, and have the capability of surviving power outages. It is further motivated by the observation that in large parallel systems, failure of processors and their caches is not unusual. Within the model we develop a framework for developing locality efficient parallel algorithms that are resilient to failures. There are several challenges, including the need to recover from failures, the desire to do this in an asynchronous setting (i.e., not blocking other processors when one fails), and the need for synchronization primitives that are robust to failures. We describe approaches to solve these challenges based on breaking computations into what we call capsules, which have certain properties, and developing a work-stealing scheduler that functions properly within the context of failures. The scheduler guarantees a time bound of $O(W/P_A + D(P/P_A) \lceil\log_{1/f} W\rceil)$ in expectation, where $W$ and $D$ are the work and depth of the computation (in the absence of failures), $P_A$ is the average number of processors available during the computation, and $f \le 1/2$ is the probability that a capsule fails. Within the model and using the proposed methods, we develop efficient algorithms for parallel sorting and other primitives.Comment: This paper is the full version of a paper at SPAA 2018 with the same nam

Gear wear process monitoring using acoustic signals

Airborne acoustic signals contain valuable information from machines and can be detected remotely for condition monitoring. However, the signal is often seriously contaminated by various noises from the environment as well as nearby machines. This paper presents an acoustic based method of monitoring a two stage helical gearbox, a common power transmission system used in various industries. A single microphone is employed to measure the acoustics of the gearbox under-going a run-to-failure test. To suppress the background noise and interferences from nearby ma-chines a modulation signal bispectrum (MSB) analysis is applied to the signal. It is shown that the analysis allows the meshing frequency components and the associated shaft modulating components to be captured more accurately to set up a clear monitoring trend to indicate the tooth wear of the gears under test. The results demonstrate that acoustic signals in conjunction with efficient signal processing methods provide an effective monitoring of the gear transmission process