A low-power quadrature digital modulator in 0.18um CMOS

Quadrature digital modulation techniques are widely used in modern communication systems because of their high performance and flexibility. However, these advantages come at the cost of high power consumption. As a result, power consumption has to be taken into account as a main design factor of the modulator.In this thesis, a low-power quadrature digital modulator in 0.18um CMOS is presented with the target system clock speed of 150 MHz. The quadrature digital modulator consists of several key blocks: quadrature direct digital synthesizer (QDDS), pulse shaping filter, interpolation filter and inverse sinc filter. The design strategy is to investigate different implementations for each block and compare the power consumption of these implementations. Based on the comparison results, the implementation that consumes the lowest power will be chosen for each block. First of all, a novel low-power QDDS is proposed in the thesis. Power consumption estimation shows that it can save up to 60% of the power consumption at 150 MHz system clock frequency compared with one conventional design. Power consumption estimation results also show that using two pulse shaping blocks to process I/Q data, cascaded integrator comb (CIC) interpolation structure, and inverse sinc filter with modified canonic signed digit (MCSD) multiplication consume less power than alternative design choices. These low-power blocks are integrated together to achieve a low-power modulator. The power consumption estimation after layout shows that it only consumes about 95 mW at 150 MHz system clock rate, which is much lower than similar commercial products. The designed modulator can provide a low-power solution for various quadrature modulators. It also has an output bandwidth from 0 to 75 MHz, configurable pulse shaping filters and interpolation filters, and an internal sin(x)/x correction filter

Extrapolation-based Path Invariants for Abstraction Refinement of Fifo Systems

Rapport de Recherche RR-1459-09 LaBRIThe technique of counterexample-guided abstraction refinement (Cegar) has been successfully applied in the areas of software and hardware verification. Automatic abstraction refinement is also desirable for the safety verification of complex infinite-state models. This paper investigates Cegar in the context of formal models of network protocols, in our case, the verification of fifo systems. Our main contribution is the introduction of extrapolation-based path invariants for abstraction refinement. We develop a range of algorithms that are based on this novel theoretical notion, and which are parametrized by different extrapolation operators. These are utilized as subroutines in the refinement step of our Cegar semi-algorithm that is based on recognizable partition abstractions. We give suffcient conditions for the termination of Cegar by constraining the extrapolation operator. Our empirical evaluation confirms the benefit of extrapolation-based path invariants

Nonlinear state-observer techniques for sensorless control of automotive PMSM's, including load-torque estimation and saliency

The paper investigates various non-linear observer-based rotor position estimation schemes for sensorless control of permanent magnet synchronous motors (PMSMs). Attributes of particular importance to the application of brushless motors in the automotive sector, are considered e.g. implementation cost, accuracy of predictions during load transients, the impact of motor saliency and algorithm complexity. Emphasis is given to techniques based on model linearisation during each sampling period (EKF); feedback-linearisation followed by Luenberger observer design based on the resulting �linear� motor characteristics; and direct design of non-linear observers. Although the benefits of sensorless commutation of PMSMs have been well expounded in the literature, an integrated approach to their design for application to salient machines subject to load torque transients remains outstanding. Furthermore, this paper shows that the inherent characteristics of some non-linear observer structures are particularly attractive since they provide a phase-locked-loop (PLL)-type of configuration that can encourage stable rotor position estimation, thereby enhancing the overall sensorless scheme. Moreover, experimental results show how operation through, and from, zero speed, is readily obtainable. Experimental results are also employed to demonstrate the attributes of each methodology, and provide dynamic and computational performance comparisons

Formal verification of dynamically reconfigurable systems

A dynamically reconfigurable system can perform complicated operations with dynamically changing the configuration. For ensuring the safety of the system, a model checking is one of the efficient formal approach. In our work, we define the specification language of a dynamically reconfigurable system and propose the model checking algorithm of verifying safety properties. © 2015 IEEE

Development of model checker of dynamic linear hybrid automata

Dynamically reconfigurable systems have attracted public attention from the point of view of miniaturization and saving power consumption for embedded systems in recent years. In this study, we propose dynamic linear hybrid automata as specification language of dynamically reconfigurable systems and the verification technique of reachability analysis. A dynamic linear hybrid automaton(DLHA) is a linear hybrid automaton extended with actions of creation and destruction. This paper presents the model checker and applies it to the model of an embedded system consisting CPU and DRP. © 2013 IEEE

Dynamic Linear Hybrid Automata and Their Applications to Formal Verification of Dynamic Reconfigurable Embedded Systems

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